TL H 10399
MF10
Universal
Monolithic
Dual
Switched
Capacitor
Filter
December 1994
MF10
Universal Monolithic Dual
Switched Capacitor Filter
General Description
The MF10 consists of 2 independent and extremely easy to
use general purpose CMOS active filter building blocks
Each block together with an external clock and 3 to 4 resis-
tors can produce various 2nd order functions Each building
block has 3 output pins One of the outputs can be config-
ured to perform either an allpass highpass or a notch func-
tion the remaining 2 output pins perform lowpass and band-
pass functions The center frequency of the lowpass and
bandpass 2nd order functions can be either directly depen-
dent on the clock frequency or they can depend on both
clock frequency and external resistor ratios The center fre-
quency of the notch and allpass functions is directly depen-
dent on the clock frequency while the highpass center fre-
quency depends on both resistor ratio and clock Up to 4th
order functions can be performed by cascading the two 2nd
order building blocks of the MF10 higher than 4th order
functions can be obtained by cascading MF10 packages
Any of the classical filter configurations (such as Butter-
worth Bessel Cauer and Chebyshev) can be formed
For pin-compatible device with improved performance refer
to LMF100 datasheet
Features
Y
Easy to use
Y
Clock to center frequency ratio accuracy
g
0 6%
Y
Filter cutoff frequency stability directly dependent on
external clock quality
Y
Low sensitivity to external component variation
Y
Separate highpass (or notch or allpass) bandpass low-
pass outputs
Y
f
O
c
Q range up to 200 kHz
Y
Operation up to 30 kHz
Y
20-pin 0 3
wide Dual-In-Line package
Y
20-pin Surface Mount (SO) wide-body package
System Block Diagram
TL H 10399 1
Connection Diagram
Surface Mount and Dual-In-Line
Package
TL H 10399 4
Top View
Order Number MF10AJ or MF10CCJ
See NS Package Number J20A
Order Number MF10ACWM or
MF10CCWM
See NS Package Number M20B
Order Number MF10ACN or
MF10CCN
See NS Package Number N20A
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
a
b
V
b
)
14V
Voltage at Any Pin
V
a
a
0 3V
V
b
b
0 3V
Input Current at Any Pin (Note 2)
5 mA
Package Input Current (Note 2)
20 mA
Power Dissipation (Note 3)
500 mW
Storage Temperature
150 C
ESD Susceptability (Note 11)
2000V
Soldering Information
N Package 10 sec
260 C
J Package 10 sec
300 C
SO Package Vapor Phase (60 Sec )
215 C
Infrared (15 Sec )
220 C
See AN-450 ``Surface Mounting Methods and Their Effect
on Product Reliability'' (Appendix D) for other methods of
soldering surface mount devices
Operating Ratings
(Note 1)
Temperature Range
T
MIN
s
T
A
s
T
MAX
MF10ACN MF10CCN
0 C
s
T
A
s
70 C
MF10CCWM MF10ACWM
0 C
s
T
A
s
70 C
MF10CCJ
b
40 C
s
T
A
s
85 C
MF10AJ
b
55 C
s
T
A
s
125 C
Electrical Characteristics
V
a
e
a
5 00V and V
b
e
b
5 00V unless otherwise specified Boldface limits
apply for T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C
MF10ACN MF10CCN
MF10CCJ MF10AJ
MF10ACWM MF10CCWM
Symbol
Parameter
Conditions
Typical
Tested
Design
Typical
Tested
Design Units
(Note 8)
Limit
Limit
(Note 8)
Limit
Limit
(Note 9) (Note 10)
(Note 9) (Note 10)
V
a
b
V
b
Supply Voltage
Min
9
9
V
Max
14
14
V
I
S
Maximum Supply
Clock Applied to Pins 10
11
8
12
12
8
12
mA
Current
No Input Signal
f
O
Center Frequency Min
f
O
c
Q
k
200 kHz
0 1
0 2
0 1
0 2
Hz
Range
Max
30
20
30
20
kHz
f
CLK
Clock Frequency
Min
5 0
10
5 0
10
Hz
Range
Max
1 5
1 0
1 5
1 0
MHz
f
CLK
f
O
50 1 Clock to
MF10A Q
e
10
V
pin12
e
5V
g
0 2
g
0 6
g
0 6
g
0 2
g
1 0
%
Center Frequency MF10C Mode 1
f
CLK
e
250 kHz
g
0 2
g
1 5
g
1 5
g
0 2
g
1 5
%
Ratio Deviation
f
CLK
f
O
100 1 Clock to
MF10A Q
e
10
V
pin12
e
0V
g
0 2
g
0 6
g
0 6
g
0 2
g
1 0
%
Center Frequency MF10C Mode 1
f
CLK
e
500 kHz
g
0 2
g
1 5
g
1 5
g
0 2
g
1 5
%
Ratio Deviation
Clock Feedthrough
Q
e
10
10
10
mV
Mode 1
Q Error (MAX)
Q
e
10
V
pin12
e
5V
g
2
g
6
g
6
g
2
g
10
%
(Note 4)
Mode 1
f
CLK
e
250 kHz
V
pin12
e
0V
g
2
g
6
g
6
g
2
g
10
%
f
CLK
e
500 kHz
H
OLP
DC Lowpass Gain
Mode 1 R1
e
R2
e
10k
0
g
0 2
g
0 2
0
g
0 2
dB
V
OS1
DC Offset Voltage (Note 5)
g
5 0
g
20
g
20
g
5 0
g
20
mV
V
OS2
DC Offset Voltage Min
V
pin12
e a
5V S
A B
e
V
a
b
150
b
185
b
185
b
150
b
185
mV
(Note 5)
Max
(f
CLK
f
O
e
50)
b
85
b
85
b
85
Min
V
pin12
e a
5V S
A B
e
V
b
b
70
b
70
mV
Max
(f
CLK
f
O
e
50)
V
OS3
DC Offset Voltage Min
V
pin12
e a
5V All Modes
b
70
b
100
b
100
b
70
b
100
mV
(Note 5)
Max
(f
CLK
f
O
e
50)
b
20
b
20
b
20
V
OS2
DC Offset Voltage
V
pin12
e
0V
S
A B
e
V
a
b
300
b
300
mV
(Note 5)
(f
CLK
f
O
e
100)
V
pin12
e
0V
S
A B
e
V
b
b
140
b
140
mV
(Note 5)
(f
CLK
f
O
e
100)
V
OS3
DC Offset Voltage
V
pin12
e
0V
All Modes
b
140
b
140
mV
(Note 5)
(f
CLK
f
O
e
100)
2
Electrical Characteristics
(Continued) V
a
e a
5 00V and V
b
e b
5 00V unless otherwise specified
Boldface limits apply for T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C
MF10ACN MF10CCN
MF10CCJ MF10AJ
MF10ACWM MF10CCWM
Symbol
Parameter
Conditions
Typical
Tested
Design
Typical
Tested
Design Units
(Note 8)
Limit
Limit
(Note 8)
Limit
Limit
(Note 9) (Note 10)
(Note 9) (Note 10)
V
OUT
Minimum Output
BP LP Pins
R
L
e
5k
g
4 25
g
3 8
g
3 8
g
4 25
g
3 8
V
Voltage Swing
N AP HP Pin R
L
e
3 5k
g
4 25
g
3 8
g
3 8
g
4 25
g
3 6
V
GBW
Op Amp Gain BW Product
2 5
2 5
MHz
SR
Op Amp Slew Rate
7
7
V ms
Dynamic Range
V
pin12
e a
5V
83
83
dB
(Note 6)
(f
CLK
f
O
e
50)
V
pin12
e
0V
80
80
dB
(f
CLK
f
O
e
100)
I
SC
Maximum Output Short Source
20
20
mA
Circuit Current (Note 7) Sink
3 0
3 0
mA
Logic Input Characteristics
Boldface limits apply for T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C
MF10ACN MF10CCN
MF10CCJ MF10AJ
MF10ACWM MF10CCWM
Parameter
Conditions
Typical
Tested
Design
Typical
Tested
Design
Units
(Note 8)
Limit
Limit
(Note 8)
Limit
Limit
(Note 9) (Note 10)
(Note 9) (Note 10)
CMOS Clock
Min Logical ``1''
V
a
e a
5V V
b
e b
5V
a
3 0
a
3 0
a
3 0
V
Input Voltage
Max Logical ``0''
V
LSh
e
0V
b
3 0
b
3 0
b
3 0
V
Min Logical ``1''
V
a
e a
10V V
b
e
0V
a
8 0
a
8 0
a
8 0
V
Max Logical ``0''
V
LSh
e a
5V
a
2 0
a
2 0
a
2 0
V
TTL Clock
Min Logical ``1''
V
a
e a
5V V
b
e b
5V
a
2 0
a
2 0
a
2 0
V
Input Voltage
Max Logical ``0''
V
LSh
e
0V
a
0 8
a
0 8
a
0 8
V
Min Logical ``1''
V
a
e a
10V V
b
e
0V
a
2 0
a
2 0
a
2 0
V
Max Logical ``0''
V
LSh
a
0 8
a
0 8
a
0 8
V
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions
Note 2
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
k
V
b
or V
IN
l
V
a
) the absolute value of current at that pin should be limited
to 5 mA or less The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four
Note 3
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
i
JA
and the ambient temperature T
A
The maximum
allowable power dissipation at any temperature is P
D
e
(T
JMAX
b
T
A
) i
JA
or the number given in the Absolute Maximum Ratings whichever is lower For this
device T
JMAX
e
125 C and the typical junction-to-ambient thermal resistance of the MF10ACN CCN when board mounted is 55 C W For the MF10AJ CCJ this
number increases to 95 C W and for the MF10ACWM CCWM this number is 66 C W
Note 4
The accuracy of the Q value is a function of the center frequency (f
O
) This is illustrated in the curves under the heading ``Typical Performance
Characteristics''
Note 5
V
OS1
V
OS2
and V
OS3
refer to the internal offsets as discussed in the Applications Information Section 3 4
Note 6
For
g
5V supplies the dynamic range is referenced to 2 82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 mV rms for
the MF10 with a 50 1 CLK ratio and 280 mV rms for the MF10 with a 100 1 CLK ratio
Note 7
The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply These are the worst case conditions
Note 8
Typicals are at 25 C and represent most likely parametric norm
Note 9
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level)
Note 10
Design limits are guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels
Note 11
Human body model 100 pF discharged through a 1 5 kX resistor
3
Typical Performance Characteristics
vs Power Supply Voltage
Power Supply Current
(N AP HP Output)
vs Load Resistance
Positive Output Voltage Swing
Resistance (N AP HP Output)
Swing vs Load
Negative Output Voltage
Swing vs Temperature
Negative Output
vs Temperature
Positive Output Swing
Frequency
Crosstalk vs Clock
Temperature
Q Deviation vs
Temperature
Q Deviation vs
Clock Frequency
Q Deviation vs
Clock Frequency
Q Deviation vs
vs Temperature
f
CLK
f
O
Deviation
vs Temperature
f
CLK
f
O
Deviation
TL H 10399 2
4
Typical Performance Characteristics
(Continued)
vs Clock Frequency
f
CLK
f
O
Deviation
vs Clock Frequency
f
CLK
f
O
Deviation
Deviation of
f
CLK
f
O
vs Nominal Q
Deviation of
f
CLK
f
O
vs Nominal Q
TL H 10399 3
Pin Descriptions
LP(1 20) BP(2 19) The second order lowpass bandpass
N AP HP(3 18)
and
notch allpass highpass
outputs
These outputs can typically sink 1 5 mA
and source 3 mA Each output typically
swings to within 1V of each supply
INV(4 17)
The inverting input of the summing op-
amp of each filter These are high im-
pedance inputs but the non-inverting in-
put is internally tied to AGND making
INV
A
and INV
B
behave like summing
junctions (low impedance current in-
puts)
S1(5 16)
S1 is a signal input pin used in the all-
pass filter configurations (see modes 4
and 5) The pin should be driven with a
source impedance of less than 1 kX If
S1 is not driven with a signal it should be
tied to AGND (mid-supply)
S
A B
(6)
This pin activates a switch that connects
one of the inputs of each filter's second
summer to either AGND (S
A B
tied to
V
b
) or to the lowpass (LP) output (S
A B
tied to V
a
) This offers the flexibility
needed for configuring the filter in its
various modes of operation
V
A
a
(7) V
D
a
(8)
Analog positive supply and digital posi-
tive supply These pins are internally
connected through the IC substrate and
therefore V
A
a
and V
D
a
should be de-
rived from the same power supply
source They have been brought out
separately so they can be bypassed by
separate capacitors
if desired
They
can be externally tied together and by-
passed by a single capacitor
V
A
b
(14) V
D
b
(13) Analog and digital negative supplies
The same comments as for V
A
a
and
V
D
a
apply here
5
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