TL F 5856
DP8303A
8-Bit
TRI-STATE
Bidirectional
Transceiver
(Inverting)
February 1996
DP8303A 8-Bit TRI-STATE
Bidirectional Transceiver (Inverting)
General Description
This family of high speed Schottky 8-bit TRI-STATE bidirec-
tional transceivers are designed to provide bidirectional
drive for bus oriented microprocessor and digital communi-
cations systems They are all capable of sinking 16 mA on
the A ports and 48 mA on the B ports (bus ports) PNP
inputs for low input current and an increased output high
(V
OH
) level allow compatibility with MOS CMOS and other
technologies that have a higher threshold and less drive
capabilities In addition they all feature glitch-free power
up down on the B port preventing erroneous glitches on the
system bus in power up or down
DP8303A and DP7304B DP8304B are featured with Trans-
mit Receive (T R) and Chip Disable (CD) inputs to simplify
control logic For greater design flexibility DP8307A and
DP7308 DP8308 are featured with Transmit (T) and
Receive (R) control inputs
Features
Y
8-bit directional data flow reduces system package
count
Y
Bidirectional TRI-STATE inputs outputs interface with
bus oriented systems
Y
PNP inputs reduce input loading
Y
Output high voltage interfaces with TTL
MOS
and
CMOS
Y
48 mA 300 pF bus drive capability
Y
Pinouts simplify system interconnections
Y
Transmit Receive and chip disable simplify control logic
Y
Compact 20-pin dual-in-line package
Y
Bus port glitch free power up down
Logic and Connection Diagrams
TL F 5856 1
Dual-In-Line Package
TL F 5856 2
Top View
Order Number DP8303AN
See NS Package Number N20A
Logic Table
Inputs
Resulting Conditions
Chip Disable
Transmit Receive
A Port
B Port
0
0
OUT
IN
0
1
IN
OUT
1
X
TRI-STATE
TRI-STATE
X
e
Don't care
TRI-STATE
is a registered trademark of National Semiconductor Corp
C1996 National Semiconductor Corporation
RRD-B30M36 Printed in U S A
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Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Output Voltage
5 5V
Maximum Power Dissipation at 25 C
Cavity Package
1667 mW
Molded Package
1832 mW
Derate cavity package 11 1 mW C above 25 C derate molded package
14 7 mW C
Storage Temperature
b
65 C to
a
150 C
Lead Temperature (soldering 4 seconds)
260 C
Recommended Operating
Conditions
Min
Max
Units
Supply Voltage (V
CC
)
DP8303A
4 75
5 25
V
Temperature (T
A
)
DP8303A
0
70
C
DC Electrical Characteristics
(Notes 2 and 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
A PORT (A0 A7)
V
IH
Logical ``1'' Input Voltage
CD
e
V
IL
T R
e
2 0V
2 0
V
V
IL
Logical ``0'' Input Voltage
CD
e
V
IL
T R
e
2 0V
0 7
V
V
OH
Logical ``1'' Output Voltage
CD
e
T R
e
V
IL
I
OH
e b
0 4 mA
V
CC
b
1 15
V
CC
b
0 7
V
V
IL
e
0 5V
I
OH
e b
3 mA
2 7
3 95
V
V
OL
Logical ``0'' Output Voltage
CD
e
T R
e
V
IL
I
OL
e
16 mA
0 35
0 5
V
V
IL
e
0 5V
I
OL
e
8 mA
0 3
0 4
V
I
OS
Output Short Circuit
CD
e
V
IL
T R
e
V
IL
V
O
e
0V
b
10
b
38
b
75
mA
Current
V
CC
e
Max (Note 4)
I
IH
Logical ``1'' Input Current
CD
e
V
IL
T R
e
2 0V V
IH
e
2 7V
0 1
80
m
A
I
I
Input Current at Maximum
CD
e
2 0V V
CC
e
Max V
IH
e
5 25V
1
mA
Input Voltage
I
IL
Logical ``0'' Input Current
CD
e
V
IL
T R
e
2 0V V
IN
e
0 4V
b
70
b
200
m
A
V
CLAMP
Input Clamp Voltage
CD
e
2 0V I
IN
e b
12 mA
b
0 7
b
1 5
V
I
OD
Output Input
CD
e
2 0V
V
IN
e
0 4V
b
200
m
A
TRI-STATE Current
V
IN
e
4 0V
80
m
A
B PORT (B0 B7)
V
IH
Logical ``1'' Input Voltage
CD
e
V
IL
T R
e
V
IL
2 0
V
V
IL
Logical ``0'' Input Voltage
CD
e
V
IL
T R
e
V
IL
0 7
V
V
OH
Logical ``1'' Output Voltage
CD
e
V
IL
T R
e
2 0V
I
OH
e b
0 4 mA
V
CC
b
1 15
V
CC
b
0 8
V
V
IL
e
0 5V
I
OH
e b
5 mA
2 7
3 9
V
I
OH
e b
10 mA
2 4
3 6
V
V
OL
Logical ``0'' Output Voltage
CD
e
V
IL
T R
e
2 0V
I
OL
e
20 mA
0 3
0 4
V
I
OL
e
48 mA
0 4
0 5
V
I
OS
Output Short Circuit
CD
e
V
IL
T R
e
2 0V V
O
e
0V
b
25
b
50
b
150
mA
Current
V
CC
e
Max (Note 4)
I
IH
Logical ``1'' Input Current
CD
e
V
IL
T R
e
V
IL
V
IH
e
2 7V
0 1
80
m
A
I
I
Input Current at Maximum
CD
e
2 0V V
CC
e
Max V
IH
e
5 25V
1
mA
Input Voltage
I
IL
Logical ``0'' Input Current
CD
e
V
IL
T R
e
V
IL
V
IN
e
0 4V
b
70
b
200
m
A
V
CLAMP
Input Clamp Voltage
CD
e
2 0V I
IN
e b
12 mA
b
0 7
b
1 5
V
I
OD
Output Input
CD
e
2 0V
V
IN
e
0 4V
b
200
m
A
TRI-STATE Current
V
IN
e
0 4V
a
200
m
A
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2
DC Electrical Characteristics
(Notes 2 and 3) (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CONTROL INPUTS CD T R
V
IH
Logical ``1'' Input Voltage
2 0
V
V
IL
Logical ``0'' Input Voltage
0 7
V
I
IH
Logical ``1'' Input Current
V
IH
e
2 7V
0 5
20
m
A
I
I
Maximum Input Current
V
CC
e
Max V
IH
e
5 25V
1 0
mA
I
IL
Logical ``0'' Input Current
V
IL
e
0 4V
T R
b
0 1
b
0 25
mA
CD
b
0 25
b
0 5
mA
V
CLAMP
Input Clamp Voltage
I
IN
e b
12 mA
b
0 8
b
1 5
V
POWER SUPPLY CURRENT
I
CC
Power Supply Current
CD
e
2 0V V
IN
V
CC
e
Max
70
100
mA
CD
e
0 4V V
INA
e
T R
e
2V V
CC
e
Max
100
150
mA
AC Electrical Characteristics
V
CC
e
5V T
A
e
25 C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
A PORT DATA MODE SPECIFICATIONS
t
PDHLA
Propagation Delay to a Logical ``0'' from
CD
e
0 4V T R
e
0 4V
(Figure A)
8
12
ns
B Port to A Port
R1
e
1k R2
e
5k C1
e
30 pF
t
PDLHA
Propagation Delay to a Logical ``1'' from
CD
e
0 4V T R
e
0 4V
(Figure A)
11
16
ns
B Port to A Port
R1
e
1k R2
e
5k C1
e
30 pF
t
PLZA
Propagation Delay from a Logical ``0'' to
B0 to B7
e
2 4V T R
e
0 4V
(Figure C)
10
15
ns
TRI-STATE from CD to A Port
S3
e
1 R5
e
1k C4
e
15 pF
t
PHZA
Propagation Delay from a Logical ``1'' to
B0 to B7
e
0 4V T R
e
0 4V
(Figure C)
8
15
ns
TRI-STATE from CD to A Port
S3
e
0 R5
e
1k C4
e
15 pF
t
PZLA
Propagation Delay from TRI-STATE to
B0 to B7
e
2 4V T R
e
0 4V
(Figure C)
20
30
ns
a Logical ``0'' from CD to A Port
S3
e
1 R5
e
1k C4
e
30 pF
t
PZHA
Propagation Delay from TRI-STATE to
B0 to B7
e
0 4V T R
e
0 4V
(Figure C)
19
30
ns
a Logical ``1'' from CD to A Port
S3
e
0 R5
e
5k C4
e
30 pF
B PORT DATA MODE SPECIFICATIONS
t
PDHLB
Propagation Delay to a Logical ``0'' from
CD
e
0 4V T R
e
2 4V
(Figure A)
12
18
ns
A Port to B Port
R1
e
100X R2
e
1k C1
e
300 pF
7
12
ns
R1
e
667X R2
e
5k C1
e
45 pF
t
PDLHB
Propagation Delay to a Logical ``1'' from
CD
e
0 4V T R
e
2 4V
(Figure A)
15
20
ns
A Port to B Port
R1
e
100X R2
e
1k C1
e
300 pF
9
14
ns
R1
e
667X R2
e
5k C1
e
45 pF
t
PLZB
Propagation Delay from a Logical ``0'' to
A0 to A7
e
2 4V T R
e
2 4V
(Figure C)
13
18
ns
TRI-STATE from CD to B Port
S3
e
1 R5
e
1k C4
e
15 pF
t
PHZB
Propagation Delay from a Logical ``1'' to
A0 to A7
e
0 4V T R
e
2 4V
(Figure C)
8
15
ns
TRI-STATE from CD to B Port
S3
e
0 R5
e
1k C4
e
15 pF
t
PLZB
Propagation Delay from TRI-STATE to
A0 to A7
e
2 4V T R
e
2 4V
(Figure C)
25
35
ns
a Logical ``0'' from CD to B Port
S3
e
1 R5
e
100X C4
e
300 pF
16
25
ns
S3
e
1 R5
e
667X C4
e
45 pF
t
PZHB
Propagation Delay from TRI-STATE to
A0 to A7
e
0 4V T R
e
2 4V
(Figure C)
22
35
ns
a Logical ``1'' from CD to B Port
S3
e
0 R5
e
1k C4
e
300 pF
14
25
ns
S3
e
0 R5
e
5kX C4
e
45 pF
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AC Electrical Characteristics
V
CC
e
5V T
A
e
25 C (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TRANSMIT RECEIVE MODE SPECIFICATIONS
t
TRL
Propagation Delay from Transmit Mode to
CD
e
0 4V
(Figure B)
Receive a Logical ``0'' T R to A Port
S1
e
1 R4
e
100X C3
e
5 pF
23
35
ns
S2
e
1 R3
e
1k C2
e
30 pF
t
TRH
Propagation Delay from Transmit Mode to
CD
e
0 4V
(Figure B)
Receive a Logical ``1'' T R to A Port
S1
e
0 R4
e
100X C3
e
5 pF
23
35
ns
S2
e
0 R3
e
5k C2
e
30 pF
t
RTL
Propagation Delay from Receive Mode to
CD
e
0 4V
(Figure B)
Transmit a Logical ``0'' T R to B Port
S1
e
1 R4
e
100X C3
e
300 pF
23
35
ns
S2
e
1 R3
e
300X C2
e
5 pF
t
RTH
Propagation Delay from Receive Mode to
CD
e
0 4V (
Figure B )
Transmit a Logical ``1'' T R to B Port
S1
e
0 R4
e
1k C3
e
300 pF
27
35
ns
S2
e
0 R3
e
300X C2
e
5 pF
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the
devices should be operated at these limits The tables of ``Electrical Characteristics'' provide conditions for actual device operation
Note 2
Unless otherwise specified min max limits apply across the supply and temperature range listed in the table of Recommended Operating Conditions
All typical values given are for V
CC
e
5V and T
A
e
25 C
Note 3
All currents into device pins are positive all currents out of device pins are negative All voltages are referenced to ground unless otherwise specified
Note 4
Only one output at a time should be shorted
Switching Time Waveforms and AC Test Circuits
TL F 5856 3
TL F 5856 4
Note
C1 includes test fixture capacitance
FIGURE A Propagation Delay from A Port to B Port or from B Port to A Port
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4
Switching Time Waveforms and AC Test Circuits
(Continued)
TL F 5856 5
TL F 5856 6
Note
C2 ad C3 include test fixture capacitance
FIGURE B Propagation Delay from T R to A Port or B Port
TL F 5856 7
TL F 5856 8
Note
C4 includes test fixture capacitance Port input is in a fixed logical condition See AC table
FIGURE C Propagation Delay to from TRI-STATE from CD to A Port or B Port
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