SCAN90CP02
1.5 Gbps 2x2 LVDS Crosspoint Switch with
Pre-Emphasis and IEEE 1149.6
General Description
The SCAN90CP02 is a 1.5 Gbps 2 x 2 LVDS crosspoint
switch. High speed data paths and flow-through pinout mini-
mize internal device jitter, while configurable 0/25/50/100%
pre-emphasis overcomes external ISI jitter effects of lossy
backplanes and cables. The differential inputs interface to
LVDS and Bus LVDS signals such as those on National's
10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and
LVPECL. The SCAN90CP02 can also be used with ASICs
and FPGAs. The non-blocking crosspoint architecture is pin-
configurable as a 1:2 clock or data splitter, 2:1 redundancy
mux, crossover function, or dual buffer for signal booster and
stub hider applications.
Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports
testability of both single-ended LVTTL/CMOS and differential
LVDS PCB interconnect. The 3.3V supply, CMOS process,
and LVDS I/O ensure high performance at low power over
the entire industrial -40 to +85C temperature range.
Features
n
1.5 Gbps per channel
n
Low power: 70 mA in dual repeater mode
@
1.5 Gbps
n
Low output jitter
n
Configurable 0/25/50/100% pre-emphasis drives lossy
backplanes and cables
n
Non-blocking architecture allows 1:2 splitter, 2:1 mux,
crossover, and dual buffer configurations
n
Flow-through pinout
n
LVDS/BLVDS/CML/LVPECL inputs, LVDS Outputs
n
IEEE 1149.1 and 1149.6 compliant
n
Single 3.3V supply
n
Separate control of inputs and outputs allows for power
savings
n
Industrial -40 to +85C temperature range
n
28-lead LLP package, or 32-lead LQFP package
Block Diagram
20071401
FIGURE 1. SCAN90CP02 Block Diagram
October 2004
SCAN90CP02
1.5
Gbps
2x2
L
VDS
Crosspoint
Switch
with
Pre-Emphasis
and
IEEE
1
149.6
2004 National Semiconductor Corporation
DS200714
www.national.com
Pin Descriptions
Pin
Name
LLP Pin
Number
LQFP
Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS COMMON TO ALL MUXES
IN0+
IN0-
9
10
9
10
I, LVDS
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
IN1+
IN1-
12
13
13
14
I, LVDS
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
SWITCHED DIFFERENTIAL OUTPUTS
OUT0+
OUT0-
27
26
32
31
O, LVDS
Inverting and non-inverting differential outputs. OUT0
can be connected to any
one pair IN0
, or IN1
. LVDS compatible (Note 2).
OUT1+
OUT1-
24
23
28
27
O, LVDS
Inverting and non-inverting differential outputs. OUT1
can be connected to any
one pair IN0
, or IN1
. LVDS compatible (Note 2).
DIGITAL CONTROL INTERFACE
SEL0,
SEL1
6
5
7
6
I, LVTTL
Select Control Inputs
EN0,
EN1
7
15
8
17
I, LVTTL
Output Enable Inputs
PEM00,
PEM01
4
3
4
3
I, LVTTL
Channel 0 Output Pre-emphasis Control Inputs
PEM10,
PEM11
2
1
2
1
I, LVTTL
Channel 1 Output Pre-emphasis Control Inputs
TDI
19
22
I, LVTTL
Test Data Input to support IEEE 1149.1 features
TDO
20
23
O, LVTTL
Test Data Output to support IEEE 1149.1 features
TMS
18
21
I, LVTTL
Test Mode Select to support IEEE 1149.1 features
TCK
17
19
I, LVTTL
Test Clock to support IEEE 1149.1 features
TRST
21
24
I, LVTTL
Test Reset to support IEEE 1149.1 features
N/C
8, 28
Not Connected
POWER
V
DD
11, 14,
16, 22,
25
12, 16,
18, 25,
29
I, Power
V
DD
= 3.3V
0.3V. At least 4 low ESR 0.01 F bypass capacitors should be
connected from V
DD
to GND plane.
GND
(Note 1) 5, 11, 15,
20, 26,
30
Ground reference to LVDS and CMOS circuitry.
For the LLP package, the DAP is used as the primary GND connection to the
device. The DAP is the exposed metal contact at the bottom of the LLP-28
package. It should be connected to the ground plane with at least 4 vias for
optimal AC and thermal performance.
Note 1: Note that for the LLP package GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the LLP package.
Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN90CP02 device have been optimized for
point-to-point backplane and cable applications.
SCAN90CP02
www.national.com
2
Connection Diagrams
20071403
LLP Top View
DAP = GND
20071404
LQFP Top View
Configuration Select Truth Table
SEL0
SEL1
EN0
EN1
OUT0
OUT1
Mode
0
0
0
0
IN0
IN0
1:2 Splitter (IN1 powered down)
0
1
0
0
IN0
IN1
Dual Channel Repeater
1
0
0
0
IN1
IN0
Dual Channel Switch
1
1
0
0
IN1
IN1
1:2 Splitter (IN0 powered down)
0
1
0
1
IN0
PD
Single Channel Repeater (Channel 1 powered down)
1
1
0
1
IN1
PD
Single Channel Switch (IN0 and OUT1 powered down)
0
0
1
0
PD
IN0
Single Channel Switch (IN1 and OUT0 powered down)
0
1
1
0
PD
IN1
Single Channel Repeater (Channel 0 powered down)
X
X
1
1
PD
PD
Both Channels in Power Down Mode
0
0
0
1
Invalid State*
1
0
0
1
Invalid State*
1
0
1
0
Invalid State*
1
1
1
0
Invalid State*
PD = Power Down mode to minimize power consumption
X = Don't Care
* Entering these states is not forbidden, however device operation is not defined in these states.
Pre-emphasis
The pre-emphasis is used to compensate for long or lossy
transmission media. Separate pins are provided for each
output to minimize power consumption. Pre-emphasis is
programmable to be off or to preset values per the Pre-
emphasis Control Selection Table.
Output Characteristics
The output characteristics of the SCAN90CP02 device have
been optimized for point-to-point backplane and cable appli-
cations.
Pre-emphasis Control Selection Table
Channel 0
Channel 1
Pre-emphasis
PEM01
PEM00
PEM11
PEM10
0
0
0
0
0%
0
1
0
1
25%
1
0
1
0
50%
1
1
1
1
100%
SCAN90CP02
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3
Applications Information
20071402
FIGURE 2. SCAN90CP02 Configuration Select Decode
SCAN90CP02
www.national.com
4
Absolute Maximum Ratings
(Note 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
)
-0.3V to +4.0V
CMOS Input Voltage
-0.3V to (V
DD
+0.3V)
LVDS Receiver Input Voltage
-0.3V to +3.6V
LVDS Driver Output Voltage
-0.3V to +3.6V
LVDS Output Short Circuit Current
40mA
Junction Temperature
+150C
Storage Temperature
-65C to +150C
Lead Temperature
(Soldering, 4sec.)
+260C
Maximum Package Power Dissipation at 25C
LLP-28
4.31 W
LQFP-32
1.47W
Derating above 25C
LLP-28
34.5 mW/C
LQFP-32
11.8 mW/C
Thermal Resistance,
JA
LLP-28
29C/W
LQFP-32
85C/W
ESD Rating
HBM, 1.5 k
, 100 pF
6.5 kV
EIAJ, 0
, 200 pF
>
250V
Recommended Operating
Conditions
Min
Typ
Max
Unit
Supply Voltage (V
DD
GND)
3.0
3.3
3.6
V
Receiver Input Voltage
0
3.6
V
Operating Free Air
Temperature
-40
25
85
C
Junction Temperature
150
C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(Note 4)
Max
Units
LVTTL DC SPECIFICATIONS (SEL0, SEL1, EN1, EN2, PEM00, PEM01, PEM10, PEM11, TDI, TCK, TMS, TRST)
V
IH
High Level Input Voltage
2.0
V
DD
V
V
IL
Low Level Input Voltage
GND
0.8
V
I
IH
High Level Input Current
V
IN
= V
DD
= V
DDMAX
-10
+10
A
I
IL
Low Level Input Current
V
IN
= V
SS
, V
DD
= V
DDMAX
-10
+10
A
I
ILR
Low Level Input Current
TDI, TMS, TRST
-40
-200
A
C
IN1
Input Capacitance
Any Digital Input Pin to V
SS
3.5
pF
C
OUT1
Output Capacitance
Any Digital Output Pin to V
SS
5.5
pF
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-1.5
-0.8
V
V
OH
High Level Output Voltage
(TDO)
I
OH
= -12 mA, V
DD
= 3.0 V
2.4
V
I
OH
= -100 A, V
DD
= 3.0 V
V
DD
-0.2
V
V
OL
Low Level Output Voltage
(TDO)
I
OL
= 12 mA, V
DD
= 3.0 V
0.5
V
I
OL
= 100 A, V
DD
= 3.0 V
0.2
V
I
OS
Output Short Circuit Current
TDO
-15
-125
mA
LVDS INPUT DC SPECIFICATIONS (IN0
, IN1
)
V
TH
Differential Input High Threshold
(Note 5)
V
CM
= 0.8V or 1.2V or 3.55V, V
DD
=
3.6V
0
50
mV
V
TL
Differential Input Low Threshold
V
CM
= 0.8V or 1.2V or 3.55V, V
DD
=
3.6V
-50
0
mV
V
ID
Differential Input Voltage
V
CM
= 0.8V to 3.55V, V
DD
= 3.6V
100
mV
V
CMR
Common Mode Voltage Range
V
ID
= 150 mV, V
DD
= 3.6V
0.05
3.55
V
C
IN2
Input Capacitance
IN+ or IN- to V
SS
3.5
pF
I
IN
Input Current
V
IN
= 3.6V, V
DD
= V
DDMAX
or 0V
-10
+10
A
V
IN
= 0V, V
DD
= V
DDMAX
or 0V
-10
+10
A
SCAN90CP02
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