SCAN92LV090
9 Channel Bus LVDS Transceiver w/ Boundary SCAN
General Description
The SCAN92LV090A is one in a series of Bus LVDS trans-
ceivers designed specifically for the high speed, low power
proprietary backplane or cable interfaces. The device oper-
ates from a single 3.3V power supply and includes nine
differential line drivers and nine receivers. To minimize bus
loading, the driver outputs and receiver inputs are internally
connected. The separate I/O of the logic side allows for loop
back support. The device also features a flow through pin out
which allows easy PCB routing for short stubs between its
pins and the connector.
The driver translates 3V TTL levels (single-ended) to differ-
ential Bus LVDS (BLVDS) output levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition, the differential signaling provides
common mode noise rejection of
1V.
The receiver threshold is less than
100 mV over a
1V
common mode range and translates the differential Bus
LVDS to standard (TTL/CMOS) levels.
This device is compliant with IEEE 1149.1 Standard Test
Access Port and Boundary Scan Architecture with the incor-
poration of the defined boundary-scan test logic and test
access port consisting of Test Data Input (TDI), Test Data
Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and
the optional Test Reset (TRST).
Features
n
IEEE 1149.1 (JTAG) Compliant
n
Bus LVDS Signaling
n
Low power CMOS design
n
High Signaling Rate Capability (above 100 Mbps)
n
0.1V to 2.3V Common Mode Range for V
ID
= 200mV
n
100 mV Receiver Sensitivity
n
Supports open and terminated failsafe on port pins
n
3.3V operation
n
Glitch free power up/down (Driver & Receiver disabled)
n
Light Bus Loading (5 pF typical) per Bus LVDS load
n
Designed for Double Termination Applications
n
Balanced Output Impedance
n
Product offered in 64 pin LQFP package and BGA
package
n
High impedance Bus pins on power off (V
CC
= 0V)
Simplified Functional Diagram
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS101242-1
April 2001
SCAN92L
V090
9
Channel
Bus
L
VDS
T
ransceiver
w/
Boundary
SCAN
2001 National Semiconductor Corporation
DS101242
www.national.com
Connection Diagram
DS101242-2
Top View
Order Number SCAN92LV090VEH
See NS Package Number VEH064DB
DS101242-16
Top View
Order Number SCAN92LV090SLC
See NS Package Number SLC64A
SCAN92L
V090
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2
Pinout Description
Pin
Name
TQFP Pin #
BGA Pin #
Input/Output
Descriptions
DO+/RI+
27, 31, 35, 37, 41,
45, 47, 51, 55
A7, B8, C6, D5, D8,
E6, F7, G5, G6
I/O
True Bus LVDS Driver Outputs and Receiver
Inputs.
DO-/RI-
26, 30, 34, 36, 40,
44, 46, 50, 54
B5, B6, C7, D6, E5,
E8, F6, G8, H7
I/O
Complimentary Bus LVDS Driver Outputs and
Receiver Inputs.
D
IN
2, 6, 12, 18, 20, 22,
58, 60, 62
A2, A4, C3, C4, D2,
E3, G3, G4, H3
I
TTL Driver Input.
RO
3, 7, 13, 19, 21, 23,
59, 61, 63
A3, B3, C1, C2, D4,
E4, F4, G1, H2
O
TTL Receiver Output.
RE
17
H1
I
Receiver Enable TTL Input (Active Low).
DE
16
G2
I
Driver Enable TTL Input (Active High).
GND
4, 5, 9, 14, 25, 56
B1, B4, D3, E1, F2,
H5
Power
Ground for digital circuitry (must connect to GND
on PC board). These pins connected internally.
V
CC
10, 15, 24, 57, 64
A1, A5, F1, F3, H4
Power
V
CC
for digital circuitry (must connect to V
CC
on
PC board). These pins connected internally.
AGND
28, 33, 43, 49, 53
A8, C5, D7, F5, G7
Power
Ground for analog circuitry (must connect to GND
on PC board). These pins connected internally.
AV
CC
29, 32, 42, 48, 52
A6, B7, C8, H6, H8
Power
Analog V
CC
(must connect to V
CC
on PC board).
These pins connected internally.
TRST
39
F8
I
Test Reset Input to support IEEE 1149.1 (Active
Low)
TMS
38
E7
I
Test Mode Select Input to support IEEE 1149.1
TCK
1
B2
I
Test Clock Input to support IEEE 1149.1
TDI
8
D1
I
Test Data Input to support IEEE 1149.1
TDO
11
E2
O
Test Data Output to support IEEE 1149.1
Description of Boundary-Scan Circuitry
The SCAN92LV090 features two unique Scan test modes,
each which requires a unique BSDL model depending on the
level of test access and fault coverage goals. In the first
mode (Mode0), only the TTL Inputs and Outputs of each
transceiver are accessible via a 1149.1 compliant protocol.
In the second mode (Mode1), the TTL Inputs and Outputs
are accessible by a 1149.1 compliant method while the
Differential I/O pins are accessible by a 1149.1 compatible
technique which evaluates the signal integrity and modifies
the data in the differential BSR as appropriate.
All test modes are handled by the ATPG software, and BSDL
selection should be invisible to the user.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
MSB
LSB (Mode0)
Instruction Code
Instruction
00000000
EXTEST
10000010
SAMPLE/PRELOAD
10000111
CLAMP
00000110
HIGHZ
All Others
BYPASS
MSB
LSB (Mode1)
Instruction Code
Instruction
10011001
EXTEST
10010010
SAMPLE/PRELOAD
10001111
CLAMP
00000110
HIGHZ
All Others
BYPASS
Bypass Register Scan Chain Definition
Logic 0
DS101242-9
Instruction Register Scan Chain Definition
DS101242-10
SCAN92L
V090
www.national.com
3
Absolute Maximum Ratings
(Notes 2, 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
4.0V
Enable Input Voltage
(DE, RE)
-0.3V to (V
CC
+0.3V)
Driver Input Voltage (D
IN
)
-0.3V to (V
CC
+0.3V)
Receiver Output Voltage
(R
OUT
)
-0.3V to (V
CC
+0.3V)
Bus Pin Voltage (DO/RI
)
-0.3V to +3.9V
ESD (HBM 1.5 k
, 100 pF)
>
4.5 kV
Driver Short Circuit Duration
momentary
Receiver Short Circuit
Duration
momentary
Maximum Package Power Dissipation at 25C
LQFP
1.74 W
Derate LQFP Package
13.9 mW/C
ja
71.7C/W
jc
10.9C/W
Junction Temperature
+150C
Storage Temperature
Range
-65C to +150C
Lead Temperature
(Soldering, 4 sec.)
260C
Recommended Operating
Conditions
Min
Max
Units
Supply Voltage (V
CC
)
3.0
3.6
V
Receiver Input Voltage
0.0
2.4
V
Operating Free Air Temperature
-40
+85
C
Maximum Input Edge Rate
(Note 6)(20% to 80%)
t/
V
Data
1.0
ns/V
Control
3.0
ns/V
DC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
V
OD
Output Differential
Voltage
R
L
= 27
,
Figure 1
DO+/RI+,
DO-/RI-
240
300
460
mV
V
OD
V
OD
Magnitude Change
27
mV
V
OS
Offset Voltage
1.1
1.3
1.5
V
V
OS
Offset Magnitude
Change
5
10
mV
V
OH
Driver Output High
Voltage
R
L
= 27
1.4
1.65
V
V
OL
Driver Output Low
Voltage
R
L
= 27
0.95
1.1
V
I
OSD
Output Short Circuit
Current (Note 10)
V
OD
= 0V, DE = V
CC
, Driver
outputs shorted together
|36|
|65|
mA
V
OH
Voltage Output High
(Note 11)
V
ID
= +300 mV
I
OH
= -400 A
R
OUT
V
CC
-0.2
V
Inputs Open
V
CC
-0.2
V
Inputs
Terminated,
R
L
= 27
V
CC
-0.2
V
V
OL
Voltage Output Low
I
OL
= 2.0 mA, V
ID
= -300 mV
0.05
0.075
V
I
OD
Receiver Output
Dynamic Current (Note
10)
V
ID
= 300mV, V
OUT
= V
CC
-1.0V
-110
|75|
mA
V
ID
= -300mV, V
OUT
= 1.0V
|75|
110
mA
V
TH
Input Threshold High
DE = 0V, V
CM
= 1.5V
DO+/RI+,
DO-/RI-
+100
mV
V
TL
Input Threshold Low
-100
mV
V
CMR
Receiver Common
Mode Range
|V
ID
|/2
2.4 -
|V
ID
|/2
V
I
IN
Input Current
DE = 0V, RE = 2.4V,
V
IN
= +2.4V or 0V
-25
1
+25
A
V
CC
= 0V, V
IN
= +2.4V or 0V
-20
1
+20
A
V
IH
Minimum Input High
Voltage
D
IN
, DE,
RE, TCK,
TRST,
TMS,
TDI
2.0
V
CC
V
V
IL
Maximum Input Low
Voltage
GND
0.8
V
SCAN92L
V090
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4
DC Electrical Characteristics
(Continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
I
IH
Input High Current
V
IN
= V
CC
or 2.4V
D
IN
, DE,
RE
-20
10
+20
A
I
IL
Input Low Current
V
IN
= GND or 0.4V
-20
10
+20
A
V
CL
Input Diode Clamp
Voltage
I
CLAMP
= -18 mA
-1.5
-0.8
V
I
IH
Input High Current
V
IN
= V
CC
TDI,
TMS,
TCK,
TRST
-20
+20
A
I
ILR
Input Low Current
V
IN
= GND, V
CC
= 3.6v
TDI,
TMS,
TRST
-25
-115
A
I
IL
Input Low Current
VIN = GND
TCK
-20
+20
A
I
CCD
Power Supply Current
Drivers Enabled,
Receivers Disabled
No Load, DE = RE = V
CC
,
DIN = V
CC
or GND
V
CC
50
80
mA
I
CCR
Power Supply Current
Drivers Disabled,
Receivers Enabled
DE = RE = 0V, V
ID
=
300mV
50
80
mA
I
CCZ
Power Supply Current,
Drivers and Receivers
TRI-STATE
DE = 0V; RE = V
CC
,
DIN = V
CC
or GND
50
80
mA
I
CC
Power Supply Current,
Drivers and Receivers
Enabled
DE = V
CC
; RE = 0V,
DIN = V
CC
or GND,
R
L
= 27
160
210
mA
I
CCS
Power Supply Current
(SCAN Test Mode),
Drivers and Receivers
Enabled
DE = V
CC
; RE = 0V,
DIN = V
CC
or GND,
R
L
= 27
, TAP in any state other
than Test-Logic-Reset
180
230
mA
I
OFF
Power Off Leakage
Current
V
CC
= 0V or OPEN,
D
IN
, DE, RE = 0V or OPEN,
V
APPLIED
= 3.6V (Port Pins)
DO+/RI+,
DO-/RI-
-20
+20
A
C
OUTPUT
Capacitance
@
Bus
Pins
DO+/RI+,
DO-/RI-
5
pF
C
OUTPUT
Capacitance
@
R
OUT
R
OUT
7
pF
AC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
t
PHLD
Differential Prop. Delay High to Low (Note 8)
R
L
= 27
,
Figure 2, Figure 3
C
L
= 10 pF
1.0
1.8
2.6
ns
t
PLHD
Differential Prop. Delay Low to High (Note 8)
1.0
1.8
2.6
ns
t
SKD1
Differential Skew |t
PHLD
t
PLHD
| (Note 9)
120
ps
t
SKD2
Chip to Chip Skew (Note 12)
1.6
ns
t
SKD3
Channel to Channel Skew (Note 13)
0.25
0.55
ns
t
TLH
Transition Time Low to High
0.5
1.2
ns
t
THL
Transition Time High to Low
0.5
1.2
ns
t
PHZ
Disable Time High to Z
R
L
= 27
,
Figure 4, Figure 5
C
L
= 10 pF
3
8
ns
t
PLZ
Disable Time Low to Z
3
8
ns
t
PZH
Enable Time Z to High
3
8
ns
t
PZL
Enable Time Z to Low
3
8
ns
SCAN92L
V090
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5
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