TL H 5070
TP3064
TP3067
``Enhanced''
Serial
Interface
CMOS
CODECFilter
COMBO
October 1991
TP3064 TP3067
``Enhanced'' Serial Interface
CMOS CODEC Filter COMBO
General Description
The TP3064 (m-law) and TP3067 (A-law) are monolithic
PCM CODEC Filters utilizing the A D and D A conversion
architecture shown in
Figure 1 and a serial PCM interface
The devices are fabricated using National's advanced dou-
ble-poly CMOS process (microCMOS)
Similar to the TP305X family these devices feature an addi-
tional Receive Power Amplifier to provide push-pull bal-
anced output drive capability The receive gain can be ad-
justed by means of two external resistors for an output level
of up to
g
6 6V across a balanced 600X load
Also included is an Analog Loopback switch and a TS
X
out-
put
See also AN-370 ``Techniques for Designing with CODEC
Filter COMBO Circuits ''
COMBO
and TRI-STATE
are registered trademarks of National Semiconductor Corpora-
tion
Features
Y
Complete CODEC and filtering system including
Transmit high-pass and low-pass filtering
Receive low-pass filter with sin x x correction
Active RC noise filters
m
-law or A-law compatible COder and DECoder
Internal precision voltage reference
Serial I O interface
Internal auto-zero circuitry
Receive push-pull power amplifiers
Y
m
-law
TP3064
Y
A-law
TP3067
Y
Designed for D3 D4 and CCITT applications
Y
g
5V operation
Y
Low operating power
typically 70 mW
Y
Power-down standby mode
typically 3 mW
Y
Automatic power-down
Y
TTL or CMOS compatible digital interfaces
Y
Maximizes line interface card circuit density
Block Diagram
TL H 5070 1
FIGURE 1
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Connection Diagrams
Dual-In-Line Package
TL H 5070 2
Top View
Plastic Chip Carrier
TL H 5070 6
Top View
Order Number TP3064J or TP3067J
See NS Package J20A
Order Number TP3064WM or TP3067WM
See NS Package M20B
Order Number TP3064N or TP3067N
See NS Package N20A
Order Number TP3064V or TP3067V
See NS Package V20A
Pin Description
Symbol
Function
VPO
a
The non-inverted output of the receive power
amplifier
GNDA
Analog ground All signals are referenced to
this pin
VPO
b
The inverted output of the receive power
amplifier
VPI
Inverting input to the receive power amplifier
VF
R
O
Analog output of the receive filter
V
CC
Positive power supply pin V
CC
e a
5V
g
5%
FS
R
Receive frame sync pulse which enables
BCLK
R
to shift PCM data into D
R
FS
R
is an
8 kHz pulse train See
Figures 2 and 3 for
timing details
D
R
Receive data input PCM data is shifted into
D
R
following the FS
R
leading edge
BCLK
R
The bit clock which shifts data into D
R
after
the FS
R
leading edge May vary from 64 kHz
CLKSEL
to 2 048 MHz Alternatively may be a logic
input which selects either
1 536 MHz 1 544 MHz or 2 048 MHz for
master clock in synchronous mode and
BCLK
X
is used for both transmit and receive
directions (see Table I)
MCLK
R
Receive master clock Must be 1 536 MHz
1 544 MHz or 2 048 MHz May be
PDN
asynchronous with MCLK
X
but should be
synchronous with MCLK
X
for best
performance When MCLK
R
is connected
continuously low MCLK
X
is selected for all
internal timing When MCLK
R
is connected
continuously high the device is powered
down
Symbol
Function
MCLK
X
Transmit master clock Must be 1 536 MHz
1 544 MHz or 2 048 MHz May be
asynchronous with MCLK
R
Best
performance is realized from synchronous
operation
BCLK
X
The bit clock which shifts out the PCM data
on D
X
May vary from 64 kHz to 2 048 MHz
but must be synchronous with MCLK
X
D
X
The TRI-STATE PCM data output which is
enabled by FS
X
FS
X
Transmit frame sync pulse input which
enables BCLK
X
to shift out the PCM data on
D
X
FS
X
is an 8 kHz pulse train see
Figures 2
and
3 for timing details
TS
X
Open drain output which pulses low during
the encoder time slot
ANLB
Analog Loopback control input Must be set
to logic `0' for normal operation When pulled
to logic `1' the transmit filter input is
disconnected from the output of the transmit
preamplifier and connected to the VPO
a
output of the receive power amplifier
GS
X
Analog output of the transmit input amplifier
Used to externally set gain
VF
X
I
b
Inverting input of the transmit input amplifier
VF
X
I
a
Non-inverting input of the transmit input
amplifier
V
BB
Negative power supply pin V
BB
e b
5V
g
5%
2
Functional Description
POWER-UP
When power is first applied power-on reset circuitry initializ-
es the COMBO
TM
and places it into a power-down state All
non-essential circuits are deactivated and the D
X
VF
R
O
VPO
b
and VPO
a
outputs are put in high impedance states
To power-up the device a logical low level or clock must be
applied to the MCLK
R
PDN pin
and FS
X
and or FS
R
pulses
must be present Thus 2 power-down control modes are
available The first is to pull the MCLK
R
PDN pin high the
alternative is to hold both FS
X
and FS
R
inputs continuously
low
the device will power-down approximately 2 ms after
the last FS
X
or FS
R
pulse Power-up will occur on the first
FS
X
or FS
R
pulse The TRI-STATE PCM data output D
X
will remain in the high impedance state until the second FS
X
pulse
SYNCHRONOUS OPERATION
For synchronous operation the same master clock and bit
clock should be used for both the transmit and receive di-
rections In this mode a clock must be applied to MCLK
X
and the MCLK
R
PDN pin can be used as a power-down
control A low level on MCLK
R
PDN powers up the device
and a high level powers down the device In either case
MCLK
X
will be selected as the master clock for both the
transmit and receive circuits A bit clock must also be ap-
plied to BCLK
X
and the BCLK
R
CLKSEL can be used to
select the proper internal divider for a master clock of 1 536
MHz 1 544 MHz or 2 048 MHz For 1 544 MHz operation
the device automatically compensates for the 193rd clock
pulse each frame
With a fixed level on the BCLK
R
CLKSEL pin BLCK
X
will be
selected as the bit clock for both the transmit and receive
directions Table I indicates the frequencies of operation
which can be selected depending on the state of BCLK
R
CLKSEL In this synchronous mode the bit clock BCLK
X
may be from 64 kHz to 2 048 MHz but must be synchro-
nous with MCLK
X
Each FS
X
pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled D
X
output on the positive edge of BCLK
X
After 8
bit clock periods the TRI-STATE D
X
output is returned to a
high impedance state With an FS
R
pulse PCM data is
latched via the D
R
input on the negative edge of BCLK
X
(or
BCLK
R
if running) FS
X
and FS
R
must be synchronous with
MCLK
X R
TABLE I Selection of Master Clock Frequencies
Master Clock
BCLK
R
CLKSEL
Frequency Selected
TP3067
TP3064
Clocked
2 048 MHz
1 536 MHz or
1 544 MHz
0
1 536 MHz or
2 048 MHz
1 544 MHz
1
2 048 MHz
1 536 MHz or
1 544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation separate transmit and receive
clocks may be applied MCLK
X
and MCLK
R
must be 2 048
MHz for the TP3067 or 1 536 MHZ 1 544 MHz for the
TP3064 and need not be synchronous For best transmis-
sion performance however MCLK
R
should be synchronous
with MCLK
X
which is easily achieved by applying only static
logic levels to the MCLK
R
PDN pin This will automatically
connect MCLK
X
to all internal MCLK
R
functions (see Pin
Description) For 1 544 MHz operation the device automati-
cally compensates for the 193rd clock pulse each frame
FS
X
starts each encoding cycle and must be synchronous
with MCLK
X
and BCLK
X
FS
R
starts each decoding cycle
and must be synchronous with BCLK
R
BCLK
R
must be a
clock the logic levels shown in Table I are not valid in asyn-
chronous mode BCLK
X
and BCLK
R
may operate from 64
kHz to 2 048 MHz
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse (the
same as the TP3020 21 CODECs) or a long frame sync
pulse Upon power initialization the device assumes a short
frame mode In this mode both frame sync pulses FS
X
and
FS
R
must be one bit clock period long with timing relation-
ships specified in
Figure 2 With FS
X
high during a falling
edge of BCLK
X
the next rising edge of BCLK
X
enables the
D
X
TRI-STATE output buffer which will output the sign bit
The following seven rising edges clock out the remaining
seven bits and the next falling edge disables the D
X
output
With FS
R
high during a falling edge of BCLK
R
(BCLK
X
in
synchronous mode) the next falling edge of BCLK
R
latches
in the sign bit The following seven falling edges latch in the
seven remaining bits All devices may utilize the short frame
sync pulse in synchronous or asynchronous operating
mode
LONG FRAME SYNC OPERATION
To use the long (TP5116A 56 CODECs) frame mode both
the frame sync pulses FS
X
and FS
R
must be three or more
bit clock periods long with timing relationships specified in
Figure 3 Based on the transmit frame sync FS
X
the COM-
BO will sense whether short or long frame sync pulses are
being used For 64 kHz operation the frame sync pulse
must be kept low for a minimum of 160 ns The D
X
TRI-
STATE output buffer is enabled with the rising edge of FS
X
or the rising edge of BCLK
X
whichever comes later and the
first bit clocked out is the sign bit The following seven
BCLK
X
rising edges clock out the remaining seven bits The
D
X
output is disabled by the falling BCLK
X
edge following
the eighth rising edge or by FS
X
going low whichever
comes later A rising edge on the receive frame sync pulse
FS
R
will cause the PCM data at D
R
to be latched in on the
next eight falling edges of BCLK
R
(BCLK
X
in synchronous
mode) All devices may utilize the long frame sync pulse in
synchronous or asynchronous mode
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors
see
Figure 4 The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized The op amp drives a unity-gain filter consisting of RC
active pre-filter followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz The output of
this filter directly drives the encoder sample-and-hold circuit
The A D is of companding type according to m-law
(TP3064) or A-law (TP3067) coding conventions A preci-
sion voltage reference is trimmed in manufacturing to pro-
vide an input overload (t
MAX
) of nominally 2 5V peak (see
3
Functional Description
(Continued)
table of Transmission Characteristics) The FS
X
frame sync
pulse controls the sampling of the filter output and then the
successive-approximation encoding cycle begins The 8-bit
code is then loaded into a buffer and shifted out through D
X
at the next FS
X
pulse The total encoding delay will be ap-
proximately 165 ms (due to the transmit filter) plus 125 ms
(due to encoding delay) which totals 290 ms Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz The decoder is A-law (TP3067) or
m
-law (TP3064) and the 5th order low pass filter corrects for
the sin x x attenuation due to the 8 kHz sample hold The
filter is then followed by a 2nd order RC active post-filter
with its output at VF
R
O The receive section is unity-gain
but gain can be added by using the power amplifiers Upon
the occurrence of FS
R
the data at the D
R
input is clocked in
on the falling edge of the next eight BCLK
R
(BCLK
X
) peri-
ods At the end of the decoder time slot the decoding cycle
begins and 10 ms later the decoder DAC output is updated
The total decoder delay is E10 ms (decoder update) plus
110 ms (filter delay) plus 62 5 ms (
frame) which gives
approximately 180 ms
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided for direct-
ly driving a matched line interface transformer The gain of
the first power amplifier can be adjusted to boost the
g
2 5V
peak output signal from the receive filter up to
g
3 3V peak
into an unbalanced 300X load or
g
4 0V into an unbal-
anced 15 kX load The second power amplifier is internally
connected in unity-gain inverting mode to give 6 dB of signal
gain for balanced loads
Maximum power transfer to a 600X subscriber line termina-
tion is obtained by differentially driving a balanced trans-
former with a
S
2 1 turns ratio as shown in
Figure 4 A total
peak power of 15 6 dBm can be delivered to the load plus
termination
ENCODING FORMAT AT D
X
OUTPUT
TP3064
TP3067
m-Law
A-Law
(Includes Even Bit Inversion)
V
IN
e a
Full-Scale
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
V
IN
e
0V
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
V
IN
e b
Full-Scale
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
4
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
V
CC
to GNDA
7V
V
BB
to GNDA
b
7V
Voltage at any Analog Input
or Output
V
CC
a
0 3V to V
BB
b
0 3V
Voltage at any Digital Input
or Output
V
CC
a
0 3V to GNDA
b
0 3V
Operating Temperature Range
b
25 C to
a
125 C
Storage Temperature Range
b
65 C to
a
150 C
Lead Temp (Soldering 10 sec )
300 C
ESD (Human Body Model) J
1000V
ESD (Human Body Model) N
1500V
Latch-Up Immunity
100 mA on Any Pin
Electrical Characteristics
Unless otherwise noted limits printed in BOLD characters are guaranteed for V
CC
e
a
5 0V
g
5% V
BB
e b
5 0V
g
5% T
A
e
0 C to 70 C by correlation with 100% electrical testing at T
A
e
25 C All other limits
are assured by correlation with other production tests and or product design and characterization All signals referenced to
GNDA Typicals specified at V
CC
e a
5 0V V
BB
e b
5 0V T
A
e
25 C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER DISSIPATION (ALL DEVICES)
I
CC
0
Power-Down Current
(Note)
0 5
1 5
mA
I
BB
0
Power-Down Current
(Note)
0 05
0 3
mA
I
CC
1
Active Current
VPI
e
0V VF
R
O VPO
a
and VPO
b
unloaded
7 0
10 0
mA
I
BB
1
Active Current
VPI
e
0V VF
R
O VPO
a
and VPO
b
unloaded
7 0
10 0
mA
DIGITAL INTERFACE
V
IL
Input Low Voltage
0 6
V
V
IH
Input High Voltage
2 2
V
V
OL
Output Low Voltage
D
X
I
L
e
3 2 mA
0 4
V
TS
X
I
L
e
3 2 mA Open Drain
0 4
V
V
OH
Output High Voltage
D
X
I
H
e b
3 2 mA
2 4
V
I
IL
Input Low Current
GNDA
s
V
IN
s
V
IL
All Digital Inputs
b
10
10
m
A
I
IH
Input High Current
V
IH
s
V
IN
s
V
CC
b
10
10
m
A
I
OZ
Output Current in High Impedance
D
X
GNDA
s
V
O
s
V
CC
b
10
10
m
A
State (TRI-STATE)
Note
I
CC0
and I
BB0
are measured after first achieving a power-up state
5
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