NTE3094
Optoisolator
Dual, High Speed, Open Collector NAND Gate
Description:
The NTE3094 consists of a pair of inverting optically coupled gates each with a GaAsP emitting diode
and a unique integrated detector. The photons are collected in the detector by a photodiode and then
amplified by a high gain linear amplifier that drives a Schottky clamped open collector output transis-
tor. each circuit is temperature, current and voltage compensated.
This unique isolator design provides maximum DC and AC circuit isolation between input and output
while achieving LSTTL/TTL circuit compatibility. The isolator operational parameters are guaranteed
from 0
to +70
C, such that a minimum input current of 5mA will sink an eight gate fanout (13mA)
at the output with 5 volt V
CC
applied to the detector. This isolation and coupling is achieved with a
typical propagation delay of 57ns.
Features:
D
LSTTL/TTL Compatible: 5V Supply
D
Ultra High Speed
D
Low Input Current Required
D
High Common Mode Rejection
D
3000V DC Withstand Test Voltage
D
Typical Data Rate 10M/Bit(s)
Absolute Maximum Ratings: (T
A
= +25
C unless otherwise specified)
Input Diode (Each Channel)
Reverse Voltage, V
R
5V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forward Current, I
F
Average
15mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak (
1ms Duration)
30mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Transistor (Each Channel)
Supply Voltage (1 Minute Maximum), V
CC
7V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage, V
O
7V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Current, I
O
16mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collector Power Dissipation, P
D
60mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total Device
Operating Temperature Range, T
opr
0
to +70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range, T
stg
55
to +125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (During Soldering, 1.6mm below seating plane, 10sec Max), T
L
+260
C
. . . . . .
Recommended Operating Conditions:
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Current, Low Level (Each Channel)
I
FL
0
250
A
Input Current, High Level (Each Channel)
I
FH
Note 1
6.3
15
mA
Supply Voltage, Output
V
CC
4.5
5.5
V
Fan Out (TTL Load)
N
8
Operating Temperature
T
A
0
70
C
Note 1. 6.3mA condition permits at least 20% CTR degradation guardband. Initial switching
threshold is 5mA or less.
Electrical Characteristics: (T
A
= 0
to +70
C, Note 2 unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
High Level Output Current
I
OH
V
CC
= 5.V, V
O
= 5.5V, I
F
= 250
A, Note 3
40
250
A
Low Level Output Voltage
V
OL
V
CC
= 5.5V, I
F
= 5mA, I
OL(sinking)
= 13mA, Note 3
0.4
0.6
V
High Level Supply Current
I
CCH
V
CC
= 5.V, I
F
= 0, (Both Channels)
15
30
mA
Low Level Supply Current
I
CCL
V
CC
= 5.V, I
F
= 10mA, (Both Channels)
27
36
mA
InputOutput Insulation
Leakage Current
I
IO
Relative Humidity = 45%, T
A
= +25
C, t = 5s,
V
IO
= 3000V DC, Note 4
1.0
A
Resistance
R
IO
V
IO
= 500V, T
A
= +25
C, Note 4
10
12
Capacitance
C
IO
f = 1MHz, T
A
= +25
C, Note 4
0.6
pF
Input Forward Voltage
V
F
I
F
= 10mA, T
A
= +25
C, Note 3, Note 5
1.5
1.75
V
Input Reverse Breakdown
Voltage
V
(BR)R
I
R
= 10
A, T
A
= +25
C
5
V
Input Capacitance
C
IN
V
F
= 0, f = 1MHz, Note 3
60
pF
Current Transfer Ratio
CTR
I
F
= 5mA, R
L
= 100
, Note 6
700
%
Resistance (InputInput)
R
II
V
II
= 500V, Note 7
10
11
Capacitance (InputInput)
C
II
f = 1MHz, Note 7
0.27
pF
Note 2. All typicals at T
A
= +25
C, V
CC
= 5V unless otherwise specified.
Note 3. Each channel.
Note 4. Measured between Pin1, Pin2, Pin3 and Pin4 shorted together and Pin5, Pin6, Pin7 and
Pin8 shorted together.
Note 5. At 10mA, V
F
decreases with increasing temperature at the rate of 1.6mV/
C.
Note 6. DC Current Transfer Ratio is defined as the ratio of the output collector current to the forward
bias input current times 100%.
Note 7. Measured between Pin1 and Pin2 shorted together and Pin3 and Pin4 shorted together.
Switching Characteristics: (T
A
= +25
C, V
CC
= 5V unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Propagation Delay Time
t
PLH
I
F
= 7.5mA, R
L
= 350
,
Note 8
57
75
ns
t
PHL
F
L
C
L
= 15pF
Note 9
45
75
ns
Output Rise Time (10% to 90%)
t
r
I
F
= 7.5mA, R
L
= 350
, C
L
= 15pF, Note 3
25
ns
Output Fall Time (90% to 10%)
t
f
F
L
L
35
ns
Common Mode Transient Immunity
CM
H
I
F
= 0mA, V
O(min)
= 2V
V
CM
= 10V
PP
,
500
V/
s
CM
L
I
F
= 7.5mA, V
O(max)
= 0.8V
CM
PP
R
L
= 350
500
V/
s
Note 3. Each channel.
Note 8. The t
PLH
propagation delay is measured from the 3.75mA point on the trailing edge of the
input pulse to the 1.5V point on the trailing edge of the output pulse.
Note 9. The t
PHL
propagation delay is measured from the 3.75mA point on the leading edge of the
input pulse to the 1.5V point on the leading edge of the output pulse.
Note10. Common mode transient immunity in Logic High level is the maximum tolerable (positive)
dv cm/dt on the leading edge of the common mode pulse (V
CM
) to assure that the output will
remain in a Logic High state (i.e. V
O
2.0V). Common mode transient immunity in Logic Low
level is the maximum tolerable (negative) dc cm/dt on the trailing edge of the common mode
pulse signal (V
CM
) to assure that the output will remain in a Logic Low state (i.e. V
O
0.8V).
V
CC
V
O
1
V
O
2
Pin Connection Diagram
.390 (9.9) Max
.250 (6.35)
Seating
Plane
1
4
8
5
.185
(4.7)
Max
.115 (2.94) Min
.100 (2.54)
.020 (.508) Min
GND
1
2
Anode 1
Cathode 1
3
Cathode 2
4
Anode 2
8
7
6
5
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