PRODUCT SPECIFICATION
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 3.1
Page 1 of 10
February 8
th
2002
10-Bit 60MSPS 0.25
m
Analog-to-Digital Converter IP
FEATURES
2.5V power supply
SNR typ 60dB for (f
in
= 10MHz)
Low power (100mW @ 2.5V and
60MSPS)
Compact area (1mm
2
)
Frequency dependent biasing
Differential input
Low input capacitance
Three power saving idle modes
APPLICATIONS
Imaging
Wireless communication
WLAN/IEEE 802.11x
DVB receivers
Powerline communication
Video products
GENERAL DESCRIPTION
The nAD1060-25 is a compact, high-speed, low power 10-bit monolithic analog-to-
digital converter, implemented in a 0.25
m single poly CMOS process with MiM
capacitor option. The converter includes a high bandwidth sample and hold. Using
internal references, the full scale range is
1V. The full scale range can be set between
0.5V and
1V using external references. It operates from a single 2.5V supply. Its
low distortion and high dynamic range offers the performance needed for demanding
imaging, multimedia, telecommunications and instrumentation applications. The bias
current level for the ADC is automatically adjusted based on the clock input
frequency. Hence, the power dissipation of the device is continuously minimised for
the current operation frequency.
The nAD1060-25 has a pipelined architecture - resulting in low input capacitance.
Digital error correction of the 9 most significant bits ensures good linearity for input
frequencies approaching Nyquist. The nAD1060-25 is compact. The core occupies
less than 1mm
2
of die area in a standard single poly 0.25
m CMOS process with MiM
capacitor option. The fully differential architecture makes it insensitive to substrate
noise. Thus it is ideal as a mixed signal ASIC macro cell.
QUICK REFERENCE DATA
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
DD
Supply voltage
2.25
2.5
2.75
V
P
D
Power dissipation
(60 MSPS)
Except digital
output drivers
100
mW
DNL
Differential nonlinearity
f
IN
=0.9991MHz
0.2
0.5
LSB
INL
Integral nonlinearity
f
IN
=0.9991MHz
0.5
1
LSB
SNR
Signal to noise ratio
f
IN
=10MHz
56
60
dB
SFDR
Spurious free dynamic
range
f
IN
=10MHz
70
dB
Table 1: Quick reference data
nAD1060-25
PRODUCT SPECIFICATION
nAD1060-25: 10 Bit 60 MSPS 0.25
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 3.1
Page 2 of 10
February 8
th
2002
ELECTRICAL SPECIFICATIONS
(
At T
A
= 25
C, V
DD
= 2.5V, Sampling Rate = 60MHz, Input frequency = 10MHz, Differential input
signal, 50% duty cycle clock and 100nF Reference decoupling unless otherwise noted
)
Symbol Parameter (condition)
Test
Level
Min.
Typ.
Max.
Units
DC Accuracy
DNL
Differential Nonlinearity
f
IN
= 0.9991 MHz
IV
0.2
0.5
LSB
INL
Integral Nonlinearity
f
IN
= 0.9991 MHz
IV
0.5
1
LSB
V
OS
Midscale offset
5.9
mV
CMRR
Common Mode Rejection Ratio
-65
dB
G
Gain Error
1
%FS
Dynamic Performance
SNR
Signal to Noise Ratio (without
harmonics)
f
IN
= 10 MHz
IV
56
56
dBFS
f
IN
= 40 MHz
IV
55
58
dBFS
SINAD
Signal to Noise and Distortion Ratio
f
IN
= 10 MHz
IV
58
dBFS
SFDR
Spurious Free Dynamic Range
f
IN
= 10 MHz
IV
60
67
dB
f
IN
= 40 MHz
IV
60
64
dB
Analog Input
V
FSR
Input Voltage Range (differential)
IV
0.5
1
V
V
CMI
Analog input common mode voltage
IV
1
1.2
1.35
V
C
INA
Input Capacitance (from each input to
ground)
1.5
pF
Reference Voltages
V
REFN
Internal reference voltage on pin 10
IV
0.7
V
V
REFP
Internal reference voltage on pin 11
IV
1.7
V
Internal reference voltage drift
100
ppm/
C
V
REFN
Negative Input Voltage (external ref)
IV
0.7
V
V
REFP
Positive Input Voltage (external ref)
IV
1.7
V
V
RR
Reference input voltage range
2)
IV
1
V
V
CM
Common mode voltage output
IV
1.2
V
Switching Performance
F
S max
Maximum Conversion Rate
IV
60
90
MSPS
F
S min
Minimum Conversion Rate
10
MSPS
Pipeline Delay
IV
6
Clocks
t
AP
Aperture delay, with bonding pad
V
1.4
ns
t
h
Output hold time, with bonding pad
V
1.9
ns
t
d
Output delay time, with bonding pad
V
4.8
ns
Digital Inputs
V
IL
Logic "0" voltage
IV
0.4
V
V
IH
Logic "1" voltage
IV
AV
DD
0.4
V
I
IL
Logic "0" current (V
I
=V
SS
)
IV
10
A
I
IH
Logic "1" current (V
I
=V
DD
)
IV
10
A
C
IND
Input Capacitance
IV
0.05
0.1
pF
(table continued on next page)
1)
Requires clock source jitter in the order of 1ps.
2)
See Figure 5.
PRODUCT SPECIFICATION
nAD1060-25: 10 Bit 60 MSPS 0.25
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 3.1
Page 3 of 10
February 8
th
2002
Digital Outputs
V
OL
Logic "0" voltage (I = 2 mA)
IV
0.2
0.4
V
V
OH
Logic "1" voltage (I = 2 mA)
IV
85% OV
DD
90% OV
DD
V
Power Supply
V
DD
Supply voltage
V
2.25
2.5
2.75
V
I
DD
Supply current (except digital output)
IV
40
mA
V
SS
Supply voltage
GND
P
D
Power dissipation (except digital output)
(active 10 MSPS)
IV
20
mW
P
D
Power dissipation (except digital output)
(active 60 MSPS)
IV
100
mW
P
D
Power dissipation (except digital output)
Power Down Mode
IV
70
W
P
D
Power dissipation (except digital output)
Sleep Mode
IV
3
mW
P
D
Power dissipation (except digital output)
Standby Mode
IV
12
mW
t
start
Start-up time from Power down
2
ms
t
start
Start-up time from Sleep mode
3
s
t
start
Start-up time from Stand By
150
ns
OV
DD
Output driver supply voltage
2.25
2.5/3.0
3.3
V
T
Junction operating temperature
-40
+85
C
Table 2: Electrical specifications
Test Levels
Test Level I: 100% production tested at +25C
Test Level II: 100% production tested at +25C and sample tested at specified
temperatures
Test Level III: Sample tested only
Test Level IV: Parameter is guaranteed by design and characterization testing
Test Level V: Parameter is typical value only
Test Level VI: 100% production tested at +25C. Guaranteed by design and
characterization testing for industrial temperature range
ABSOLUTE MAXIMUM RATINGS
Supply voltages
AV
DD
............................... - 0.3V to +3V
DV
DD1
................. - 0.3V to V
DD
+ 0.3V
OV
DD
................... - 0.3V to V
DD
+ 0.3V
Input voltages
Analog In ......... - 0.3V to AV
DD
+ 0.3V
Digital In ............. - 0.3V to V
DD
+ 0.3V
REF
P
................. - 0.3V to AV
DD
+ 0.3V
REF
N
................ - 0.3V to AV
DD
+ 0.3V
CLOCK............... - 0.3V to V
DD
+ 0.3V
Temperatures
Operating Temperature....-40 to +85
C
Storage Temperature.....-65 to +125
C
Note: Stress above one or more of the limiting values may cause permanent damage
to the device.
PRODUCT SPECIFICATION
nAD1060-25: 10 Bit 60 MSPS 0.25
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 3.1
Page 4 of 10
February 8
th
2002
PIN FUNCTIONS
Pin Name
Description
INP, INN
Differential input signal pins. Common mode voltage: V
CMI
(See Electrical specifications)
REFP, REFN
Reference pins (output/bypass). Bypass with 100nF capacitors close to the pins. (See
Application Information)
BIAS0, BIAS1,
RBIAS, PD
Operating mode and bias control pins. (See Modes of operation)
CLOCK
ADC Clock
BIAS_CLOCK
Clock used for bias current generation
VCM
Common mode voltage output
BITO[9:0]
Digital outputs ( MSB to LSB)
OVR
Over-Range flag
EXTREF
Disables internal voltage references. External voltages must be applied to REFN and REFP.
VDD
Digital power
AVDD
Analog power
AVSS
Analog and digital ground
Table 3: Pin functions
IP BLOCK LAYOUT
IP_footprint
REFP
REFN
B
I
A
S
1
B
I
A
S
0
P
D
V
C
M
I
N
P
I
N
N
CLOCK
O
V
R
B
I
T
O
[
9
:
0
]
AVSS
AVDD
AVSS
AVDD
VDD
Y
=
7
1
1
u
m
AVSS
AVDD
AVSS
AVDD
VDD
VDD
VDD
E
X
T
R
E
F
R
B
I
A
S
BIAS_CLOCK
X=1208um
Figure 1: Size and pin placement for nAD1060-25 IP
FUNCTIONAL BLOCK DIAGRAM
CURRENT
BIAS
VOLTAGE
REFERENCE
DIGITAL
CLOCK
DRIVER
PIPELINE CHAIN
INN
INP
REFP
REFN
E
X
T
R
E
F
R
B
I
A
S
B
I
A
S
0
B
I
A
S
1
P
D
B
I
A
S
_
C
L
O
C
K
C
L
O
C
K
B
I
T
O
[
9
:
0
]
O
V
R
VCM
Figure 2: Functional Block diagram nAD1060-25
PRODUCT SPECIFICATION
nAD1060-25: 10 Bit 60 MSPS 0.25
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 3.1
Page 5 of 10
February 8
th
2002
MODES OF OPERATION
The ADC has four different modes of operation, controlled as described in Table 4:
Digital control and clock settings
Mode of operation
BIAS0
BIAS1
RBIAS
PD
BIAS_CLOCK
CLOCK
Active
HIGH
HIGH
LOW
LOW
Running
Running
Standby
LOW
LOW
LOW
LOW
Running
Stopped
Sleep
LOW
LOW
HIGH
LOW
Stopped
Stopped
Power down
LOW
LOW
LOW
HIGH
Stopped
Stopped
Table 4: Control settings for ADC operational modes
Active mode
In the active mode, the ADC is fully functional.
A performance versus power consumption trade off can be made by adding or
subtracting 12.5% of the pipeline bias current with the bias1 and bias0 pins:
BIAS0
BIAS1
CURRENT
1
0
-12.5%
0
1
+12.5%
1
1:
Typical
Idle modes
In the three idle modes, the ADC is not functional. The different modes are
distinguished primary by power consumption and start-up time. Start-up time is
defined as the time it takes for the ADC to reach full performance in active mode
when switched from an idle mode. Refer to `Electrical Specifications' for power
consumption and start-up times for the different modes.
While the start-up times for standby and sleep modes are constant, the start-up time in
power down mode will be proportional to Off-Chip REFP,REFN decoupling. The
amount of decoupling on the REFP and REFN will have impact on the performance
(see Characterization report).
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