OBJECTIVE PRODUCT SPECIFICATION
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.3
Page 1 of 11
September 11
th
, 2001
12-Bit 80MSPS Sampling
Analog-to-Digital Converter
FEATURES
3.3V power supply
SINAD min 63.2dB for f
in
=
50MHz
Low power (353mW @ 3.3V and
80MSPS)
Frequency dependent biasing
Internal, wideband Track/Hold
Differential input
Low input capacitance
Power Down and Sleep Mode
APPLICATIONS
Imaging
Test equipment
Computer scanners
Wireless communication
Powerline communication
Set top boxes
Video products
GENERAL DESCRIPTION
The nAD1280-18T is a compact, high-speed, low power 12-bit monolithic analog-to-
digital converter, implemented in a 0.18
m single poly CMOS process with MiM
capacitors and thick oxide transistor option. It has 12-bit resolution with 11 effective
bits at low input frequencies, and close to 12 bit dynamic range for video frequency
signals. The converter includes a high bandwidth track and hold. Using internal
references, the full scale range is
1V. The full scale range can be set between
0.75V and
1.0V using external references. It operates from a single 3.3V supply,
while I/O is biased with 1.8V. Its low distortion and high dynamic range offers the
performance needed for demanding imaging, multimedia, telecommunications and
instrumentation applications. The bias current level for the ADC is automatically
adjusted based on the clock input frequency. Hence, the power dissipation of the
device is continuously minimised for the current operation frequency.
QUICK REFERENCE DATA
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
DD
Supply voltage
2.97
3.3
3.63
V
I
DD
Supply current (80 MSPS)
107
mA
P
D
Power dissipation (15
MSPS)
Except digital output
drivers
80
mW
P
D
Power dissipation (80
MSPS)
Except digital output
drivers
353
mW
DNL
Differential nonlinearity
f
IN
=0.9991MHz
0.5
LSB
INL
Integral nonlinearity
f
IN
=0.9991MHz
1.0
LSB
f
S
Conversion rate
80
MHz
N
Resolution
12
bit
Table 1. Quick reference data
nAD1280-18T
OBJECTIVE PRODUCT SPECIFICATION
nAD1280-18T 12 Bit 80 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.3
Page 2 of 11
September 11
th
, 2001
GENERAL DESCRIPTION (Continued)
The nAD1280-18T has a pipelined architecture - resulting in low input capacitance.
Digital error correction of the 11 most significant bits ensures good linearity for input
frequencies approaching Nyquist. The nAD1280-18T is compact. The core occupies
less than 4mm
2
of die area in the TSMC MiM 0.18
m CMOS process with thick
oxide option. The fully differential architecture makes it insensitive to substrate noise.
Thus it is ideal as a mixed signal ASIC macro cell.
BLOCK DIAGRAM
ANALOG1280
-18T
CORR_LOG
ANCL
OCK
BIT<11:0>
IN_CORR<19:0>
CKBUS<3:0>
ADC_CLK
REF_
HI
R
E
F_LO
BIAS0
BIAS1
nAD1280-18T
CLOCKBUF
REF_SEL
CKCORR<1:0>
CK0
CK0B
CK2
CK2B
IN_N
IN_P
SCR_EN
OR_
H
I
O
R
_LO
CM
Figure 1. Block diagram nAD1280-18T
OBJECTIVE PRODUCT SPECIFICATION
nAD1280-18T 12 Bit 80 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.3
Page 3 of 11
September 11
th
, 2001
ELECTRICAL SPECIFICATIONS
(
At T
A
= 25
C, V
DD
= 3.3V, Sampling Rate = 80MHz, Input frequency = 15MHz, Differential input
signal, 50% duty cycle clock unless otherwise noted
)
Symbol Parameter (condition)
Test
Level
Min.
Typ.
Max.
Units
DC Accuracy
DNL
Differential Nonlinearity
f
IN
= 0.9991 MHz
IV
0.5
LSB
INL
Integral Nonlinearity
f
IN
= 0.9991 MHz
IV
1.0
LSB
V
OS
Midscale offset
1
%FS
CMRR
Common Mode Rejection Ratio
TBD
dB
G
Gain Error
2
5
%FS
Dynamic Performance
SNR
Signal to Noise Ratio (without
harmonics)
f
IN
= 10 MHz
IV
68
dBFS
f
IN
= 50 MHz
IV
63.2
dBFS
SINAD
Signal to Noise and Distortion Ratio
f
IN
= 10 MHz
IV
66
dBFS
f
IN
= 50 MHz
IV
63.2
SFDR
Spurious Free Dynamic Range
f
IN
= 10 MHz
IV
75
dB
f
IN
= 50 MHz
IV
70
dB
Analog Input
V
FSR
Input Voltage Range (differential)
IV
0.75
1.0
TBD
V
V
CMI
Common mode input voltage
IV
1.65
V
C
INA
Input Capacitance (from each input to
ground)
150
FF
Reference Voltages
Internal reference voltage drift
100
ppm/
C
V
REFNO
Negative Input Voltage
IV
1.05
1.15
TBD
V
V
REFPO
Positive Input Voltage
IV
TBD
2.15
2.25
V
V
REFP
-V
REFN
Reference input voltage range
1)
IV
0.75
0.75
TBD
V
V
CM
Common mode output voltage
IV
TBD
1.65
TBD
V
Switching Performance
F
S
Conversion Rate
IV
80
MSPS
Pipeline Delay
IV
6
Clocks
t
AP
Aperture delay, IP
V
0.3
ns
t
h
Output hold time, IP
V
2.0
ns
t
d
Output delay time, IP
V
2.7
ns
t
AP
Aperture delay, with bonding pad
V
TBD
ns
t
h
Output hold time, with bonding pad
V
TBD
ns
t
d
Output delay time, with bonding pad
V
TBD
ns
Digital Inputs
V
IL
Logic "0" voltage
IV
0.4
V
V
IH
Logic "1" voltage
IV
1.62
1.8
1.98
V
I
IL
Logic "0" current (V
I
=V
SS
)
IV
10
A
I
IH
Logic "1" current (V
I
=V
DD
)
IV
10
A
C
IND
Input Capacitance
IV
TBD
pF
(table continued on next page)
OBJECTIVE PRODUCT SPECIFICATION
nAD1280-18T 12 Bit 80 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.3
Page 4 of 11
September 11
th
, 2001
Digital Outputs
V
OL
Logic "0" voltage (I = 2 mA)
IV
0.2
0.4
V
V
OH
Logic "1" voltage (I = 2 mA)
IV
85% OV
DD
90% OV
DD
V
Power Supply
V
DD
Supply voltage
V
2.97
3.3
3.63
V
I
DD
Supply current (except digital output)
IV
107
mA
V
SS
Supply voltage
GND
P
D
Power dissipation (except digital output)
(15 MSPS)
IV
80
mW
P
D
Power dissipation (except digital output)
(80 MSPS)
IV
353
mW
P
D
Power dissipation (except digital output)
Power Down Mode
2)
IV
TBD
W
P
D
Power dissipation (except digital output)
Sleep Mode
IV
TBD
W
AV
DD
-
DV
DD1
Analog power digital power pins
-0.2
+0.2
V
OV
DD
Output driver supply voltage
1.62
1.8
1.98
V
T
Ambient operating temperature
-40
+85
C
Table 2. Electrical specifications
1)
See Figure 5.
2)
Power Down Mode is only available for IP version of nAD1280-18T.
Test Levels
Test Level I: 100% production tested at +25C
Test Level II: 100% production tested at +25C and sample tested at specified
temperatures
Test Level III: Sample tested only
Test Level IV: Parameter is guaranteed by design and characterization testing
Test Level V: Parameter is typical value only
Test Level VI: 100% production tested at +25C. Guaranteed by design and
characterization testing for industrial temperature range
ABSOLUTE MAXIMUM RATINGS
Supply voltages
AV
DD
............................- 0.2V to +2.2V
DV
DD1
..................- 0.2V to V
DD
+ 0.2V
OV
DD
...................- 0.2V to V
DD
+ 0.2V
Input voltages
Analog In.......... - 0.2V to AV
DD
+ 0.2V
Digital In..............- 0.2V to V
DD
+ 0.2V
REF
P
................. - 0.2V to AV
DD
+ 0.2V
REF
N
................ - 0.2V to AV
DD
+ 0.2V
CLOCK ............... - 0.2V to V
DD
+ 0.2V
Temperatures
Operating Temperature ....-40 to +85
C
Storage Temperature.. ... - 65 to +125
C
Note: Stress above one or more of the limiting values may cause permanent damage
to the device.
OBJECTIVE PRODUCT SPECIFICATION
nAD1280-18T 12 Bit 80 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.3
Page 5 of 11
September 11
th
, 2001
PIN FUNCTIONS
Pin Name
Description
IN
P
IN
N
Differential input signal pins. Common mode voltage: 2.5V
REF
HI
REF
LO
Reference input pins. Bypass with 100nF capacitors close to the pins. See Application
Information below.
BIAS0, BIAS1
Digital inputs for max. sampling rate programming.
BIAS1=0, BIAS0=0: Sleep mode (power save)
BIAS1=0, BIAS0=1: - 12.5% bias
BIAS1=1, BIAS0=0: +12.5% bias
BIAS1=1, BIAS0=1: Typ. Bias
The bias setting is automatically performed based on the clock input frequency. This
function should be used ONLY if another bias setting than typical must be used.
ADC_CLK
Clock input
CM
Common mode voltage output
BIT11 - BIT0
Digital outputs ( MSB to LSB)
SCR_EN
Enable scrambling algorithm
REF_SEL
Disable internal references
OR_HI, OR_LO
Overflow HIGH input
Overflow LOW input
V
DD
Power pins for on chip power
V
SS
Ground pins
OV
DD
Power pins for output drivers
Table 3. Pin functions
PIN ASSIGNMENT
(TBD)
Figure 2. Pin assignment for the package used for samples
IP BLOCK LAYOUT
(TBD)
Figure 3. Size and pin placement for nAD1280-18T.
The height and width of the layout is X =2000
m and Y=1550
m respectively in the
0.18
m CMOS process.
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