Preliminary
No.
Electronic Components
KGL4222C 12.5-Gbps 1:16 DEMUX
1. DESCRIPTION
KGL 4222C converts one data stream into 16bit parallel data operating over 12.5GHz clock frequency. The KGL
4222C is fabricated by OKI 0.2
m gate length GaAs MESFETs process. By using of OKI unique flip-flops, which are
MCFF(
M
emory
C
ell type
F
lip
F
lop) and CBFF(
C
ommon gate
B
ias
F
lip
F
lop), high speed operation and low power
dissipation are realized. Capacitive coupling is recommended for clock input connection and data input connection. Low
speed signal interfaces are compatible with ECL. The device is mounted in 48pin package
2. ABSOLUTE MAXIMUM RATINGS
No.
Item
Symbol
Min.
Max.
Units
1
Supply Voltage
VTT
-2.3
0.3
V
2
Clock and Data Input Voltage
VCDI
-2.3
-0.5
V
3
Package Base Temperature under Bias
Ts
-45
100
C
4
Storage Temperature
Tst
-45
125
C
3. FUNCTIONAL BLOCK DIAGRAM
LCKN
1/2
divider
1:8
DEMUX
controller
1:2
DEMUX
Figure 1 Block Diagram of KGL4222 C
Q0
Q2
Q4
QE
1/2CK
delay
1/2CK
HCK
DAT
Q1
Q3
Q5
QF
1:8
DEMUX
LCK
8
control pulses
delay
1/2CK
1/16CK
Preliminary
No.
4.
RECOMMENDED OPERATING CONDITIONS
Item
Symbol
Min.
Typ.
Max.
Units
Power Supply
VTT
-2.1
-2.0
-1.9
V
Operating Temperature Range at Package Base
Ts
0
70
C
5.
ELECTRICAL CHARACTERISTICS
5-1. AC CHARACTERISTICS
VTT=-2V
0.1V, Ts = 0~70C
Item
Symbol
Test Condition
Min.
Typ.
Max.
Units
Clock Period
t
C
80
-
-
ps
Set-up Time ( DAT to HCK )
t
DS
Input clock period : 80ps
TBD
-13
TBD
ps
Hold Time (HCK to DAT)
t
DH
Input clock period : 80ps
TBD
33
TBD
ps
HCK-DAT Phase Margin
t
M
Input clock period : 80ps
30
40
72
ps
LCK to Output Data Delay
t
C16Q
Input clock period : 80ps
0
45
90
ps
Valid
Valid
t
M
t
DS
t
DH
t
C
HCK
DAT
LCK
LCKN
Q
0
~Q
F
t
C16Q
Figure 2 Waveforms of KGL4222 C
Valid
Preliminary
No.
HCK
Q0
Q1
Q2
Q3
Q4
QE
QF
LCK
LCKN
O2
O1
P2
P1
E2
E1
C2
C1
D2
D1
B2
B1
A2
A1
Figure 3 Time Chart of KGL4222 C
DAT
O1
A2
C2
O2
A3 C3
P1
B2
P2
B3
5-2. DC CHARACTERISTICS
VTT=
-2V0.1V, Ts = 0~70C
Item
Symbol
Test Condition
Min. Typ. Max. Units
Power Dissipation
PW
2.2
2.8
W
Clock Input Voltage Swing (HCK)
VCKI
TBD
1.0
TBD Vpp
Data Input Voltage Swing (DAT)
VDI
0.5
0.7
1.2
Vpp
Low level of Data Output (Q0 ~QF)
VDOL
50 to VTT
-1.95 -1.8
-1.6
V
High level of Data Output (Q0 ~QF)
VDOH
50 to VTT
-1.1
-0.9
-0.75
V
Low Level of 1/16 clock Output (LCN, LCKN)
VCOL
50 to VTT
-1.95 -1.8
-1.55
V
High Level of 1/16 clock Output (LCN, LCKN)
VCOH
50 to VTT
-1.15 -0.93 -0.75
V
Preliminary
No.
6.
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
13 14
15
16
17
18
19
20
21
22
23
24
VTT
Q0
Q2
Q4
Q6
VTT
G
Q8
QA
QC
QE
VTT
VTT
Q1
Q3
Q5
Q7
G
VTT
Q9
QB
QD
QF
VTT
G
LCKN
G
LCK
G
VTT
VTT
G
DAT
G
DAR
G
G
G
G
G
G
VTT
VTT
G
HCK
G
HCR
G
(Top View)
Note: 1 G is a ground terminal.
2 HCR is a reference bias terminal of clock. Usually HCR is
connected to VTT through a capacitor (100nF).
Figure 4 PIN A ssignment of KGL4222C
Preliminary
No.
7.
PACKAGE DIMENSIONS
37
13.97
unit : mm
17.41 SQ.
15.57 SQ.
12.00 SQ.
13
25
1
1.80
0.7
0.5
0.6 0
2
0.3
0.125
0.05
Figure 5 48pin Package Dimensions
0.40
0.05
1.27
8.
TYPICAL INTERFACE CONFIGURATION
VDOH=-0.93V,VDOL=-1.8V
VCOH=-0.93V,VCOL=-1.8V
Zo=50
28
HCK
G
1,3,5,8,10,12,18,
25,27,29,32,33,
34,35,36,42
VTT
VTT
VTT
VTT
VTT
-2V
6,7,13,19,
24,30,31,
37,43,48
Q0
LCK
47
23
4
2
Zo=50
Zo=50
Zo=50
Zo=50
50
50
50
50
QF
LCKN
Zo=50
9
DAT
Figure 6 Typical Interfacing Configuration of KGL4222 C
50
50
VDI=0.8 Vpp
VCKI= 0.8 Vpp
VTT
HCR
26
100nF
KGL4222C
VTT
DAR
11
100nF
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