Semiconductor
MSM51V16165D/DSL
1/17
DESCRIPTION
The MSM51V16165D/DSL is a 1,048,576-word 16-bit dynamic RAM fabricated in Oki's silicon-
gate CMOS technology. The MSM51V16165D/DSL achieves high integration, high-speed operation,
and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
double-layer metal CMOS process. The MSM51V16165D/DSL is available in a 42-pin plastic SOJ or
50/44-pin plastic TSOP. The MSM51V16165DSL (the self-refresh version) is specially designed for
lower-power applications.
FEATURES
1,048,576-word 16-bit configuration
Single 3.3 V power supply,
0.3 V tolerance
Input
: LVTTL compatible, low input capacitance
Output : LVTTL compatible, 3-state
Refresh : 4096 cycles/64 ms, 4096 cycles/128 ms (SL version)
Fast page mode with EDO, read modify write capability
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
CAS before RAS self-refresh capability (SL version)
Package options:
42-pin 400 mil plastic SOJ
(SOJ42-P-400-1.27)
(Product : MSM51V16165D/DSL-xxJS)
50/44-pin 400 mil plastic TSOP
(TSOPII50/44-P-400-0.80-K) (Product : MSM51V16165D/DSL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Semiconductor
MSM51V16165D/DSL
1,048,576-Word
16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
MSM51V16165D/DSL-70 70 ns
124 ns
84 ns
288 mW
360 mW
Family
Access Time (Max.)
Cycle Time
(Min.)
Standby (Max.)
Power Dissipation
MSM51V16165D/DSL-50
t
RAC
50 ns
35 ns
t
AA
25 ns
20 ns
t
CAC
13 ns
20 ns
t
OEA
13 ns
MSM51V16165D/DSL-60 60 ns
104 ns
324 mW
30 ns
15 ns
15 ns
Operating (Max.)
1.8 mW/
0.72 mW (SL version)
Preliminary
E2G0132-17-61
This version: Mar. 1998
Semiconductor
MSM51V16165D/DSL
2/17
PIN CONFIGURATION (TOP VIEW)
Note :
The same power supply voltage must be provided to every V
CC
pin, and the same GND
voltage level must be provided to every V
SS
pin.
Pin Name
Function
A0 - A7,
Address Input
RAS
Row Address Strobe
LCAS
Lower Byte Column Address Strobe
DQ1 - DQ16
Data Input/Data Output
OE
Output Enable
WE
Write Enable
V
CC
Power Supply (3.3 V)
NC
No Connection
A8R - A11R
UCAS
Upper Byte Column Address Strobe
V
SS
Ground (0 V)
A9R
A8R
A7
A6
A5
A4
A11R
A10R
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
21
22
30
31
32
33
34
35
36
37
38
39
40
41
42
V
CC
DQ1
DQ2
DQ3
DQ4
V
CC
DQ5
DQ6
DQ7
DQ8
NC
NC
WE
V
CC
V
SS
UCAS
LCAS
NC
DQ9
DQ10
DQ11
DQ12
V
SS
DQ13
DQ14
DQ15
DQ16
V
SS
14
29
RAS
OE
15
28
A11R
A9R
16
27
A10R
A8R
17
26
A0
A7
18
25
A1
A6
19
24
A2
A5
20
23
A3
A4
1
2
3
4
5
6
7
8
9
10
11
25
26
40
41
42
43
44
45
46
47
48
49
50
V
CC
DQ1
DQ2
DQ3
DQ4
V
CC
DQ5
DQ6
DQ7
DQ8
NC
V
CC
V
SS
NC
DQ9
DQ10
DQ11
DQ12
V
SS
DQ13
DQ14
DQ15
DQ16
V
SS
15
36
NC
NC
16
35
NC
LCAS
17
34
WE
UCAS
18
33
RAS
OE
19
32
20
31
21
30
22
29
23
28
24
27
42-Pin Plastic SOJ
50/44-Pin Plastic TSOP
(K Type)
Semiconductor
MSM51V16165D/DSL
4/17
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Recommended Operating Conditions
Capacitance
*: Ta = 25
C
Voltage on Any Pin Relative to V
SS
Short Circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
V
T
Symbol
I
OS
P
D
*
T
opr
T
stg
0.5 to 4.6
50
1
0 to 70
55 to 150
Rating
mA
W
C
C
Parameter
V
Unit
Power Supply Voltage
Input High Voltage
Input Low Voltage
V
CC
Symbol
V
SS
V
IH
V
IL
3.3
0
--
--
Typ.
Parameter
3.0
0
2.0
0.3
Min.
3.6
0
V
CC
+ 0.3
0.8
Max.
(Ta = 0C to 70C)
V
Unit
V
V
V
Input Capacitance
(A0 - A7, A8R - A11R)
Input Capacitance
Output Capacitance (DQ1 - DQ16)
C
IN1
Symbol
C
IN2
C
I/O
5
7
7
Max.
pF
Unit
pF
pF
Parameter
(V
CC
= 3.3 V 0.3 V, Ta = 25C, f = 1 MHz)
--
--
--
Typ.
(
RAS, LCAS, UCAS, WE, OE)
Semiconductor
MSM51V16165D/DSL
5/17
DC Characteristics
Parameter
Symbol
Condition
MSM51V16165
D/DSL-50
MSM51V16165
D/DSL-60
MSM51V16165
D/DSL-70
(V
CC
= 3.3 V 0.3 V, Ta = 0C to 70C)
I
OH
= 2.0 mA
Output High Voltage
I
OL
= 2.0 mA
Output Low Voltage
0 V V
I
V
CC
+ 0.3 V;
All other pins not
Input Leakage Current
under test = 0 V
DQ disable
Output Leakage Current
0 V V
O
V
CC
RAS, CAS cycling,
Average Power
t
RC
= Min.
Supply Current
(Operating)
RAS, CAS = V
IH
Power Supply
RAS, CAS
Current (Standby)
RAS cycling,
Average Power
CAS = V
IH
,
Supply Current
t
RC
= Min.
(
RAS-only Refresh)
RAS = V
IH
,
Power Supply
CAS = V
IL
,
Current (Standby)
DQ = enable
Average Power
CAS before RAS
Supply Current
(
CAS before RAS Refresh)
Average Power
RAS 0.2 V,
Supply Current
CAS 0.2 V
(
CAS before RAS
V
OH
V
OL
I
LI
I
LO
I
CC1
I
CC2
I
CC3
I
CC5
I
CC6
I
CCS
V
CC
0.2 V
Min.
Max.
Min.
Max.
Min.
Max.
Unit Note
RAS cycling,
2.4
0
10
10
--
--
--
--
--
--
--
V
CC
0.4
10
10
75
2
0.5
75
75
300
5
2.4
0
10
10
--
--
--
--
--
--
--
V
CC
0.4
10
10
70
2
0.5
70
70
300
5
2.4
0
10
10
--
--
--
--
--
--
--
V
CC
0.4
10
10
65
2
0.5
65
65
300
5
--
200
--
200
--
200
V
V
mA
mA
mA
mA
mA
mA
mA
mA
1, 2
1, 2
1, 2
1, 5
1
1
mA
1, 5
t
RC
= 31.3 ms,
Average Power
CAS before RAS,
Supply Current
t
RAS
1 ms
(Battery Backup)
I
CC10
--
400
--
400
--
400
mA
1, 4,
RAS = V
IL
,
Average Power
CAS cycling,
Supply Current
t
HPC
= Min.
(Fast Page Mode)
I
CC7
--
100
--
90
--
80
mA
1, 3
5
Self-Refresh)
Notes : 1. I
CC
Max. is specified as I
CC
for output open condition.
2. The address can be changed once or less while RAS = V
IL
.
3. The address can be changed once or less while CAS = V
IH
.
4. V
CC
0.2 V V
IH
V
CC
+ 0.3 V, 0.3 V V
IL
0.2 V.
5. SL version.
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