1/37
Semiconductor
MSM80C88A-10RS/GS/JS
GENERAL DESCRIPTION
The MSM80C88A-10 is internal 16-bit CPUs with 8-bit interface implemented in Silicon Gate
CMOS technology. It is designed with the same processing speed as the NMOS8088-1, but with
considerably less power consumption.
The processor has attributes of both 8 and 16-bit microprocessor. It is directly compatible with
MSM80C86A-10 software and MSM80C85AH hardware and peripherals.
FEATURES
8-Bit Data Bus interface
16-Bit Internal Architecture
1 Mbyte Direct Addressable Memory Space
Software Compatible with MSM80C86A-10
Internal 14-Word by 16-bit Register Set
24-Operand Addressing Modes
Bit, Byte, Word and String Operations
8 and 16-bit Signed and Unsigned Arithmetic Operation
From DC to 10 MHz Clock Rate (Note)
Low Power Dissipation (10mA/MHz)
Bus Hold Circuitry Eliminated Pull-Up Resistors
40-pin Plastic DIP (DIP 40-P-600-2.54): (Product name: MSM80C88A-10RS)
44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM80C88A-10JS)
56-pin Plastic QFP (QFP56-P-1519-1.00-K): (Product name: MSM80C88A-10GS-K)
(Note) 10 MHz Spec. is not compatible with Intel 8088-1 spec.
Semiconductor
MSM80C88A-10RS/GS/JS
8-Bit CMOS MICROPROCESSOR
E2O0011-27-X2
This version: Jan. 1998
Previous version: Aug. 1996
2/37
Semiconductor
MSM80C88A-10RS/GS/JS
FUNCTIONAL BLOCK DIAGRAM
SS
0
Exeuction Unit
Register File
Relocation
Register File
Data
Pointer
and
Index
Registers
(8 Words)
Segment
Registers
and
Instruction
Pointer
(5 Words)
16Bit ALU
Flags
Bus
Interface
Unit
AD
7
- AD
0
INTA, RD, WR, IO/M
DT/R, DEN, ALE
12
8
4
3
4-byte
Instruction
Queue
LOCK
QS
0
, QS
1
S
2
, S
1
, S
0
GND
V
CC
2
3
3
MN/MX
READY
RESET
CLK
TEST
INTR
NMI
RQ/GT
0
, 1
HOLD
HLDA
2
Control & Timing
Bus Interface Unit
A
19
/ S
6
A
8
.
.
.
3/37
Semiconductor
MSM80C88A-10RS/GS/JS
PIN CONFIGURATION (TOP VIEW)
40 pin Plastic DIP
16
15
14
13
GND
20
19
18
17
GND
1
2
3
4
5
6
7
8
9
10
11
12
32
31
30
29
28
27
26
37
38
39
40
36
35
34
33
25
RESET
A
15
A
16
/S
3
A
17
/S
4
A
18
/S
5
A
19
/S
6
SS
0
(HIGH)
MN/MX
RD
HOLD(RQ/GT0)
HLDA(RQ/GT1)
WR(LOCK)
IO/M(S
2
)
DT/R(S
1
)
DEN(S
0
)
ALE(QS
0
)
INTA(QS
1
)
TEST
READY
24
23
22
21
V
CC
NMI
INTR
CLK
A
9
A
8
AD
7
AD
6
AD
5
AD
4
AD
3
AD
2
AD
1
AD
0
A
14
A
13
A
12
A
11
A
10
56
A
11
NC
HOLD(RQ/GT0)
NC
42
41
40
39
38
37
36
NC
A
19
/S
6
SS
0
(HIGH)
MN/MX
RD
35
34
33
32
31
30
29
NC
HLDA(RQ/GT1)
WR(LOCK)
IO/M(S
2
)
DT/R(S
1
)
DEN(S
0
)
1
2
3
4
5
6
7
NC
A
10
A
9
A
8
AD
7
AD
6
NC
8
9
10
11
12
13
14
NC
AD
5
AD
4
AD
3
AD
2
AD
1
AD
0
56 pin Plastic QFP
39
38
37
36
35
34
33
NC
A19/S6
HIGH FIX(SS0)
MN/MX
RD
HOLD(RQ/GT0)
HLDA(RQ/GT1)
A
10
A
9
A
8
AD
7
AD
6
AD
5
AD
4
18
19
20
21
22
23
24
NC
NM1
INTR
CLK
GND
NC
RESET
6
5
4
3
2
1
44
A
11
A
12
A
13
A
14
GND
NC
7
8
9
10
11
12
13
32
31
30
29
WR(LOCK)
M/IO(S
2
)
DT/R(S
1
)
AD
3
AD
2
AD
1
AD
0
14
15
16
17
DEN(S
0
)
V
CC
25
26
27
28
READY
TEST
(
INTA
)QS
1
(ALE)QS
0
43
42
41
40
A
15
A
16
/S
3
A
17
/S
4
A
18
/S
5
44 pin Plastic QFJ
55
A
12
54
A
13
53
A
14
52
NC
51
GND
50
NC
49
V
CC
48
V
CC
47
NC
46
A
15
45
A
16
/S
3
44
A
17
/S
4
43
A
18
/S
5
15
NMI
16
INTR
17
CLK
18
NC
19
NC
20
GND
21
V
CC
22
NC
23
NC
24
RESET
25
READY
26
TEST
27
INTA
(QS
1
)
28
ALE(QS
0
)
4/37
Semiconductor
MSM80C88A-10RS/GS/JS
ABSOLUTE MAXIMUM RATING
65 to +150
MSM80C88A-10RS
Power Supply Voltage
V
CC
0.5 to +7
V
Input Voltage
V
IN
0.5 to V
CC
+0.5
V
Output Voltage
V
OUT
0.5 to V
CC
+0.5
V
Storage Temperature
T
STG
C
Power Dissipation
P
D
0.7
W
Parameter
Units
Symbol
With respect
to GND
--
Ta = 25C
Condition
Rating
MSM80C88A-10GS MSM80C88A-10JS
1.0
OPERATING RANGE
Range
Power Supply Voltage
V
CC
4.75 to 5.25
V
Operating Temperature
T
op
0 to +70
C
Parameter
Unit
Symbol
RECOMMENDED OPERATING CONDITIONS
Typ.
Power Supply Voltage
V
CC
5.0
V
T
op
+25
"L" Input Voltage
V
IL
V
IL
--
"H" Input Voltage
*1
--
Min.
4.75
0
0.5
V
CC
-0.8
Max.
5.25
+70
+0.8
V
CC
+0.5
Parameter
Unit
Symbol
C
V
V
*2
--
2.0
V
CC
+0.5
V
Operating Temperature
*1 Only CLK
*2 Except CLK
5/37
Semiconductor
MSM80C88A-10RS/GS/JS
DC CHARACTERISTICS
Max.
"L" Output Voltage
V
OL
0.4
V
"H" Output Voltage
V
OH
--
V
Parameter
Unit
Symbol
Min.
--
3.0
V
CC
0.4
I
OL
= 2.5 mA
I
OH
= 2.5 mA
I
OH
= 100 mA
Conditions
Input Leak Current
I
LI
+1.0
mA
Output Leak Current
I
LO
+10
mA
1.0
10
0
V
IN
V
CC
V
O
= V
CC
or GND
Typ.
Input Leakage Current
(Bus Hold Low)
I
BHL
400
mA
50
V
IN
= 0.8 V
*3
Input Leakage Current
(Bus Hold High
I
BHH
400
mA
50
V
IN
= 3.0 V
*4
Bus Hold Low Overdrive
I
BHLO
600
mA
--
*5
Bus Hold High Overdrive
I
BHHO
600
mA
--
*6
Operating Power
Supply Current
I
CCS
10
Standby Power
Current
I
CC
500
--
--
V
IL
= GND
V
IH
= V
CC
V
IN
= V
CC
or GND
Outputs Unloaded
CLK = GND or V
CC
mA/MHz
mA
Input Capacitance
C
IN
10
pF
Output Capacitance
C
OUT
15
pF
--
--
I/O Capacitance
C
I/O
20
--
--
--
--
--
--
--
--
--
--
--
--
--
pF
*7
*7
*7
--
(V
CC
= 4.5 to 5.5 V, Ta = 40C to +85C)
*3 Test conditions are to lower V
IN
to GND and then raise V
IN
to 0.8 V on pins 2-16, and 35-39.
*4 Test conditions are to raise V
IN
to V
CC
and then lower V
IN
to 3.0 V on pins 2-16, 26-32, and 34-
39.
*5 An external driver must source at least I
BHLO
to switch this node from LOW to HIGH.
*6 An external driver must sink at least I
BHHO
to switch this node from HIGH to LOW.
*7 Test Conditions: a) Freq = 1 MHz.
b) Ummeasured Pins at GND.
c) V
IN
at 5.0 V or GND.
6/37
Semiconductor
MSM80C88A-10RS/GS/JS
AC CHARACTERISTICS
Minimum Mode System
Timing Requirements
Parameter
Symbol
Unit
Max.
Min.
10 MHz Spec.
V
CC
= 4.75 V to 5.25 V
Ta = 0 to +70C
Data in Setup Time
T
DVCL
20
--
ns
Data in Hold Time
T
CLDX
10
--
ns
Max.
Min.
8 MHz Spec.
V
CC
= 4.75 V to 5.25 V
Ta = 0 to +70C
20
--
10
--
Max.
Min.
5 MHz Spec.
V
CC
= 4.5 V to 5.5 V
Ta = -40 to +85C
30
--
10
--
CLK Rise Time
(From 1.0 V to 3.5 V)
T
CH1CH2
--
10
ns
--
10
--
10
CLK Fall Time
(From 3.5 V to 1.0 V)
T
CL2CL1
--
10
ns
--
10
--
10
CLK Cycle Period
T
CLCL
100
DC
ns
CLK Low Time
T
CLCH
46
--
ns
CLK High Time
T
CHCL
44
--
ns
125
DC
68
--
44
--
200
DC
118
--
69
--
READY Setup Time into
MSM80C88A-10
T
RYHCH
46
--
ns
READY Hold Time into MSM80C88A-10 T
CHRYX
20
--
ns
68
--
20
--
118
--
30
--
RDY Setup Time into
MSM 82C84A-2 (See Notes 1, 2)
T
R1VCL
35
--
ns
35
--
35
--
RDY Hold Time into MSM 82C84A-2
(See Notes 1, 2)
T
CLR1X
0
--
ns
0
--
0
--
HOLD Setup Time
T
HVCH
20
--
ns
20
--
35
--
READY inactive to CLK
(See Note 3)
T
RYLCL
8
--
ns
8
--
8
--
T
IHIL
--
15
ns
--
15
--
15
INTR, NMI, TEST Setup Time
(See Note 2)
T
INVCH
15
--
ns
15
--
30
--
Input Rise Time (Except CLK)
(From 0.8 V to 2.0 V)
T
ILIH
--
15
ns
--
15
--
15
Input Fall Time (Except CLK)
(From 2.0 V to 0.8 V)
7/37
Semiconductor
MSM80C88A-10RS/GS/JS
Timing Responses
RD Inactive Delay
t
CLRH
10
60
ns
RD Inactive to Next Address Active
t
RHAV
t
CLCL
-35
--
ns
HLDA Valid Delay
t
CLHAV
10
60
ns
10
80
t
CLCH
-40
--
10
100
10
150
t
CLCH
-45
--
10
160
RD Width
t
RLRH
2t
CLCL
-40
--
ns
2t
CLCL
-50
--
2t
CLCL
-75
--
WR Width
t
WLWH
2t
CLCL
-35
--
ns
2t
CLCL
-40
--
2t
CLCL
-60
--
Address Valid to ALE Low
t
AVAL
t
CLCH
-35
--
ns
t
CLCH
-40
--
t
CLCH
-60
--
Ouput Rise Time (From 0.8 V to 2.0 V) t
OLOH
--
15
ns
--
15
--
15
Output Fall Time (From 2.0 V to 0.8 V)
t
OHOL
--
15
ns
--
15
--
15
Parameter
Symbol
Unit
Max.
Min.
10 MHz Spec.
V
CC
= 4.75 V to 5.25 V
Ta = 0 to +70C
Max.
Min.
8 MHz Spec.
V
CC
= 4.75 V to 5.25 V
Ta = 0 to +70C
Max.
Min.
5 MHz Spec.
V
CC
= 4.5 V to 5.5 V
Ta = 40 to +85C
Address Valid Delay
t
CLAV
10
60
ns
Address Hold Time
t
CLAX
10
--
ns
Address Float Delay
t
CLAZ
t
CLAX
50
ns
10
60
10
--
t
CLAX
50
10
110
10
--
t
CLAX
80
ALE Width
t
LHLL
t
CLCH
-10
--
ns
t
CLCH
-10
--
t
CLCH
-20
--
ALE Active Delay
t
CLLH
--
40
ns
--
50
--
80
ALE Inactive Delay
t
CHLL
--
45
ns
--
55
--
85
Address Hold Time to ALE Inactive
t
LLAX
t
CLCH
-10
--
ns
t
CLCH
-10
--
t
CLCH
-10
--
Data Valid Delay
t
CLDV
10
60
ns
--
60
10
110
Data Hold Time
t
CHDX
10
--
ns
--
--
10
--
Data Hold Time after WR
t
WHDX
t
CLCH
-25
--
ns
t
CLCH
-30
--
t
CLCH
-30
--
Control Active Delay 1
t
CVCTV
10
55
ns
10
70
10
110
Control Active Delay 2
t
CHCTV
10
50
ns
10
60
10
110
Control Inactive Delay
t
CVCTX
10
55
ns
10
70
10
110
Address Float to RD Active
t
AZRL
0
--
ns
0
--
0
--
RD Active Delay
t
CLRL
10
70
ns
10
100
10
165
Notes: 1. Signals at MSM82C84A-2 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next
CLK.
3. Applies only to T
2
state. (8 ns into T
3
)
8/37
Semiconductor
MSM80C88A-10RS/GS/JS
Maximum Mode System (Using MSM82C88-2 Bus Controller)
Timing Requirements
Parameter
Symbol
Unit
Max.
Min.
10 MHz Spec.
V
CC
= 4.75 V to 5.25 V
Ta = 0 to +70C
Data in Setup Time
t
DVCL
20
--
ns
Data in Hold Time
t
CLDX
10
--
ns
Max.
Min.
8 MHz Spec.
V
CC
= 4.75 V to 5.25 V
Ta = 0 to +70C
20
--
10
--
Max.
Min.
5 MHz Spec.
V
CC
= 4.5 V to 5.5 V
Ta = 40 to +85C
30
--
10
--
CLK Rise Time
(From 1.0 V to 3.5 V)
t
CH1CH2
--
10
ns
--
10
--
10
CLK Fall Time
(From 3.5 V to 1.0 V)
t
CL2CL1
--
10
ns
--
10
--
10
CLK Cycle Period
t
CLCL
100
DC
ns
CLK Low Time
t
CLCH
46
--
ns
CLK High Time
t
CHCL
44
--
ns
125
DC
68
--
44
--
200
DC
118
--
69
--
READY Setup Time into
MSM80C88A-10
t
RYHCH
46
--
ns
READY Hold Time into MSM80C88A-10 t
CHRYX
20
--
ns
68
--
20
--
118
--
30
--
RDY Setup Time into
MSM 82C84A-2 (See Notes 1, 2)
t
R1VCL
35
--
ns
35
--
35
--
RDY Hold Time into MSM82C84A-2
(See Notes 1, 2)
t
CLR1X
0
--
ns
0
--
0
--
READY inactive to CLK
(See Note 3)
t
RYLCL
8
--
ns
8
--
8
--
t
IHIL
--
15
ns
--
15
--
15
Input Rise Time (Except CLK)
(From 0.8 V to 2.0 V)
t
ILIH
--
15
ns
--
15
--
15
Input Fall Time (Except CLK)
(From 2.0 V to 0.8 V)
RQ/GT Setup Time
t
GVCH
15
--
ns
15
--
30
--
RQ Hold Time into MSM80C88A-10
t
CHGX
20
--
ns
30
--
40
--
Setup Time for Recognition (NMI,
INTR, TEST) (See Note 2)
t
INVCH
15
--
ns
15
--
30
--
9/37
Semiconductor
MSM80C88A-10RS/GS/JS
Timing Responses
Parameter
Symbol
Unit
Max.
Min.
10 MHz Spec.
V
CC
= 4.75 V to 5.25 V
Ta = 0 to +70C
Max.
Min.
8 MHz Spec.
V
CC
= 4.75 V to 5.25 V
Ta = 0 to +70C
Max.
Min.
5 MHz Spec.
V
CC
= 4.5 V to 5.5 V
Ta = 40 to +85C
Command Active Delay (See Note 1)
t
CLML
5
35
ns
Command Inactive Delay (See Note 1)
t
CLMH
5
45
ns
READY Active to Status Passive
(See Note 4)
t
RYHSH
--
45
ns
5
35
5
45
--
65
5
45
5
45
--
110
Status Inactive Delay
Status Active Delay
t
CHSV
10
45
ns
10
60
10
110
Address Valid Delay
t
CLSH
10
60
ns
10
70
10
130
Address Hold Time
t
CLAV
10
60
ns
10
60
10
110
Address Float Delay
t
CLAX
10
--
ns
10
--
10
--
Status Valid to ALE High (See Note 1)
t
CLAZ
t
CLAX
50
ns
t
CLAX
50
t
CLAX
80
Status Valid to MCE High (See Note 1)
t
SVLH
--
25
ns
--
25
--
35
CLK Low to ALE Valid (See Note 1)
t
SVMCH
--
30
ns
--
30
--
35
CLK Low to MCE High (See Note 1)
t
CLLH
--
25
ns
--
25
--
35
ALE Inactive Delay (See Note 1)
t
CLMCH
--
25
ns
--
25
--
35
Data Valid Delay
t
CHLL
4
25
ns
4
25
4
35
Data Hold Time
t
CLDV
10
60
ns
10
60
10
110
t
CHDX
10
--
ns
10
--
10
--
Control Active Delay (See Note 1)
t
CVNV
5
45
ns
Control Inactive Delay (See Note 1)
t
CVNX
5
45
ns
5
45
5
45
5
45
5
45
RD Active Delay
Address Float to RD Active
t
AZRL
0
--
ns
0
--
0
--
RD Inactive Delay
t
CLRL
10
70
ns
10
100
10
165
RD Inactive to Next Address Active
t
CLRH
10
60
ns
10
80
10
150
t
RHAV
t
CLCL
-35
--
ns
t
CLCL
-40
--
t
CLCL
-45
--
t
CHDTL
--
50
ns
--
50
--
50
GT Active Delay (See Note 5)
GT Inactive Delay
t
CLGL
0
45
ns
0
50
0
85
RD Width
t
CLGH
0
45
ns
0
50
0
85
Output Rise Time (From 0.8 V to 2.0 V)
t
RLRH
2t
CLCL
-40
--
ns
2t
CLCL
-50
--
2t
CLCL
-75
--
Output Fall Time (From 2.0 V to 0.8 V)
t
OLOH
--
15
ns
--
15
--
15
t
OHOL
--
15
ns
--
15
--
15
Direction Control Active Delay
(See Note 1)
t
CHDTH
--
30
ns
--
30
--
35
Direction Control Inactive Delay
(See Note 1)
Notes: 1. Signals at MSM82C84A-2 or MSM82C88-2 are shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next
CLK.
3. Applies only to T
2
state (8 ns into T
3
)
4. Applies only to T
3
and wait states.
5. C
L
= 40 pF (RQ/GT
0
, RQ/GT
1
)
10/37
Semiconductor
MSM80C88A-10RS/GS/JS
A.C. Testing Input, Output Waveform
A.C. Testing Load Circuit
Test Points
1.5
0.45
1.5
2.4
A.C. Testing: Inputs are driven at 2.4 V
for a logic "1" and 0.45 V for a logic
"0" timing measurements are 1.5 V for
both a logic "1" and "0".
C
L
= 100 pF
C
L
includes jig capacitance.
Device
Under
Test
TIMING CHART
Minimum Mode
V
IH
V
IL
IO/M, SS
0
A
19
/S
6
- A
16
/S
3
ALE
RDY (MSM82C84A-2 Input)
See NOTE 4
READY (MSM80C88A-10 Input)
Read Cycle
(NOTE 1)
(WR, INTA = VOH)
AD
7
- AD
0
RD
DT/R
DEN
t
CHCTV
t
CHCL
t
CLCL
t
CH1CH2
t
CL2CL1
T
1
T
2
T
3
Tw
T
4
t
CLCH
t
CHDX
t
CLDV
t
CLAX
t
CLAV
t
CLLH
t
LHLL
t
LLAX
t
AVAL
t
CHLL
t
R1VCL
A
19
- A
16
S
6
- S
3
t
CLR1X
t
RYLCL
t
CHRYX
t
RYHCH
t
CLDX
t
DVCL
t
CLAZ
t
CLAX
t
CLAV
AD
7 -
AD
0
t
AZRL
t
CHCTV
t
CLRL
t
CVCTV
t
CVCTX
t
RLRH
t
CHCTV
t
CLRH
t
RHAV
Data In
Float
A
15
- A
8
(Float during INTA)
V
IH
V
IL
CLK (MSM82C84A-2 Output)
A
15
- A
8
t
LLAX
t
AVAL
Float
11/37
Semiconductor
MSM80C88A-10RS/GS/JS
Minimum Mode (continued)
Notes: 1. All signals switch between V
OH
and V
OL
unless otherwise specified.
2. RDY is sampled near the end of T
2
, T
3
, TW to determine if TW machines states are
to be inserted.
3. Two INTA cycles run back-to-back. The MSM80C88A-10 LOCAL ADDR/DATA
BUS is floating during both INTA cycles. Control signals shown for second INTA
cycle.
4. Signals at MSM82C84A-2 shown for reference only.
5. All timing measurements are made at 1.5 V unless otherwise noted.
V
IH
V
IL
IO/M, SS
0
A
19
/S
6
- A
16
/S
3
ALE
AD
7
- AD
0
DEN
WR
AD
7
- AD
0
DT/R
INTA
DEN
Write Cycle
(NOTE 1)
RD, INTA
DT/R = V
OH
INTA Cycle
(NOTES 1 & 3)
(RD, WR = V
OH
BHE = V
OL
)
CLK (MSM82C84A-2 Output)
t
CLCL
t
CHCTV
t
CHCL
t
CH1CH2
t
CL2CL1
T
2
T
3
T
4
T
W
t
CLCH
t
CLAV
t
CLLH
t
CLAX
t
CLDV
t
CHDX
A
19
-
A
16
S
6
-
S
3
t
LHLL
t
LLAX
t
AVAL
t
CLDV
t
CLAV
t
CVCTV
t
LLAX
t
AVAL
t
CVCTV
t
WLWH
t
CLAZ
t
CHCTV
t
CVCTV
t
CVCTV
t
CVCTX
t
CLAV
t
CHCTV
t
CLDX
t
CVCTX
t
DVCL
t
CVCTX
t
CHDX
AD
7
-
AD
0
Data Out
Float
Pointer
Float
Invalid Address
Software Halt
RD, WR, INTA = V
OH
DT/R = Indeterminate
t
CLAX
t
WHDX
Software Halt T
CLAV
t
CHLL
12/37
Semiconductor
MSM80C88A-10RS/GS/JS
Maximum Mode
,,
V
IH
V
IL
QS
0
, QS
1
A
19
/S
6
- A
16
/S
3
S
2
, S
1
, S
0
(Except Halt)
ALE
(MSM82C88-2 Output)
RDY
(MSM82C84A-2 Input)
See
NOTE 5
READY
(MSM80C88A-10 Input)
Read Cycle
AD
7
- AD
0
RD
MRDC or
IORC
DEN
DT/R
MSM82C88-2
Outputs
See NOTES 5, 6
t
CLAV
t
CLCL
t
CH1CH2
t
CL2CL1
T
w
T
1
T
2
T
3
T
4
t
CHCL
t
CLCH
t
CHSV
t
CLSH
t
CLAV
t
CLAX
t
CLDV
t
CHDX
t
SVLH
t
CLLH
t
CHLL
t
RYLCL
t
R1VCL
t
CLR1X
t
CHRYX
t
RYHSH
t
RYHCH
t
CLAZ
t
DVCL
t
RHAV
t
CHDTH
t
CLMH
t
CVNX
t
RLRH
t
CVNV
t
CLML
t
CLRL
t
CHDTL
t
CLAV
t
CLRH
t
CLDX
t
AZRL
A
19
- A
16
(See NOTE 8)
Data In
Float
AD
7
- AD
0
A
15
- A
8
S
6
- S
3
Float
V
IH
V
IL
t
CLAX
CLK (MSM82C84A-2 Output)
A
15
- A
8
13/37
Semiconductor
MSM80C88A-10RS/GS/JS
Maximum Mode (continued)
Notes: 1. All signals switch between V
OH
and V
OL
unless otherwise specified.
2. RDY is sampled near the end of T
2
, T
3
, T
W
to determine if T
W
machines states are to
be inserted.
3. Cascade address is valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The MSM80C86A-10 LOCAL ADDR/DATA
BUS is floating during both INTA cycles. Control for pointer address is shown for
second INTA cycle.
5. Signal at MSM82C84A-2 or MSM82C88-2 shown for reference only.
The issuance of the MSM82C88-2 command and control signals (MRDC, MWTC,
AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high MSM82C88-2
CEN.
7. All timing measurements are made at 1.5 V unless otherwise noted.
8. Status inactive in state just prior to T
4
.
V
IH
V
IL
AD
7
- AD
0
A
15
- A
8
(See NOTES 3 & 4)
CLK (MSM82C84A-2 Outputs)
S
2
, S
1
, S
0
(Except Halt)
MSM82C88-2 Outputs
See NOTES 5, 6
MSM82C88-2 Outputs
See NOTES 5, 6
INTA Cycle
t
CHSV
T
1
DEN
ANMC or AIOWC
MWTC or IOWC
MCE/
PDEN
AD
7
- AD
0
DT/R
INTA
DEN
Write Cycle
AD
7
- AD
0
, A
15
- A
8
S
2
, S
1
, S
0
Software Halt
(DEN V
OL
; RD, MRDC, IORC, MWTC, AMWC,
IOWC, AIOWC, INTA V
OH
)
t
CLAV
t
CLSH
t
CLAX
t
CLDV
t
CVNX
t
CLML
t
CLMH
t
CLML
t
CLMH
t
DVCL
t
CLDX
t
CHDTH
t
CLMH
t
CVNX
t
CVNV
t
CLAV
t
CLML
t
CHDTL
t
CLMCH
t
SVMCH
t
CVNX
t
CLAZ
t
CVNV
Data
(See
NOTE 8)
Pointer
Float
Float
Float
Reserved for
Cascade ADDR
Float
AD
7
- AD
0
T
2
T
3
T
w
T
4
Invalid Address
t
CHDX
14/37
Semiconductor
MSM80C88A-10RS/GS/JS
Asynchronous Signal Recognition
Hold/Hold Acknowledge Timing (Minimum Mode Only)
Request/Grant Sequence Timing (Maximum Mode Only)
CLK
Signal
NMI
INTR
TEST
t
INVCH
(See NOTE 1)
NOTE: 1 Setup requirements for asynchronous
signals only to guarantee recognition
at next CLK
Bus Lock Signal Timing (Maximum Mode Only)
Reset Timing
CLK
LOCK
t
CLAV
Any CLK Cycle
Any CLK Cycle
t
CLAV
50msec
t
DVCL
CLK
t
CLDX
Reset
V
CC
4 CLK Cycles
CLK
HOLD
AD
7
- AD
0
, A
15
- A
8
A
19
/S
6
- A
16
/S
3
RD
IO/M
DT/R, WR, DEN
HLDA
MSM80C88A-10
Coprocessor
MSM80C88A-10
1 CLK Cycle
1 or 2 Cycles
t
HVCH
t
HVCH
t
CLHAV
t
CLHAV
t
CLAZ
Any CLK Cycle
CLK
RQ/GT
AD
7
- AD
0
, A
15
- A
8
A
19
/S
6
- A
16
/S
3
S
2
, S
1
, S
0
,
RD, COCK
t
CLGH
t
CLCL
t
GVCH
t
CHGX
t
CLGL
t
CLCL
t
CLGH
Previous Grant
t
CLAZ
Pulse 3
Coprocessor
Release
MSM80C88A-10
Coprocessor
MSM80C88A-10
(See NOTE 1)
NOTE: 1 The coprocessor may not drive the busses outside
the region shown without risking contention
Pulse 1
Coprocessor
RQ
Pulse 2
MSM80C88
GT
> 0 CLK Cycle
15/37
Semiconductor
MSM80C88A-10RS/GS/JS
PIN DESCRIPTION
AD
0
- AD
7
ADDRESS DATA BUS: Input/Output
These lines are the multiplexed address and data bus.
These are the address bus at T
1
cycle and the data bus at T
2
, T
3
, T
W
and T
4
cycle.
T
2
, T
3
, T
W
and T
4
cycle.
These lines are high impedance during interrupt acknowledge and hold acknowledge.
A
8
- A
15
ADDRESS BUS: Output
These lines are the address bus bits 8 thru 15 at all cycles.
These lines do not have to be latched by an ALE signal.
These lines are high impedance during interrupt acknowledge and hold acknowledge.
A
16
/S
3
, A
17
/S
4
, A
18
/S
5
, A
19
/S
6
ADDRES/STATUS : Output
These are the four most significant address as at the T
1
, cycle.
Accessing I/O port address, these are low at T
1
Cycle.
These lines are Status lines at the T
2
, T
3
, T
W
and T
4
Cycles.
S
5
indicates interrupt enable Flag.
S
3
and S
4
are encoded as shown below.
These lines are high impedance during hold acknowledge.
RD
READ: Output
This line indicates that CPU is in a memory or I/O read cycle.
This line is the read strobe signal when CPU reads data from a memory or I/O device. This
line is active low.
This line is high impedance during hold acknowledge.
READY
READY:Input
This line indicates to the CPU that the addressed memory or I/O device is ready to read or
write.
This line is active high. If the setup and hold time are out of specification, an illegal operation
will occur.
INTR
INTERRUPT REQUEST: Input
This line is the level triggered interrupt request signal which is sampled during the last clock
cycle of instruction and string manipulations.
It can be internally masked by software.
This signal is active high and internally synchronized.
1
0
1
Stack
0
Alternate Data
S
3
0
1
1
0
S
4
Characteristics
Code or None
Data
16/37
Semiconductor
MSM80C88A-10RS/GS/JS
TEST
TEST: Input
This line is examined by a "WAIT" instruction.
When TEST is high, the CPU enters an idle cycle.
When TEST is low, the CPU exits in an idle cycle.
NMI
NON MASKABLE INTERRUPT: Input
This line causes a type 2 interrupt.
NMI is not maskable.
This signal is internally synchronized and needs 2-clock cycle pulse width.
RESET
RESET:Input
This signal causes the CPU to initialize immediately.
This signal is active high and must be at least four clock cycles.
CLK
CLOCK: Input
This signal provides the basic timing for the internal circuit.
MN/MX
MINIMUM/MAXIMUM: Input
This signal selects the CPU's operating mode.
When V
CC
is connected, the CPU operates in minimum mode.
When GND is connected, the CPU operates in maximum mode.
V
CC
V
CC
: +5V supplied.
GND
GROUND
The following pin function descriptions are for maximum mode only. Other pin functions are
already described.
S
O
, S
1
, S
2
STATUS: Output
These lines indicate bus status and they are used by the MSM82C88-2 Bus Controller to
generate all memory and I/O access control signals. These lines are high impedance during
hold acknowledge. These status lines are encoded as shown below.
0
0
0
Read I/O Port
0 (LOW)
Interrupt acknowledge
S
2
0
1
1
0
S
1
Characteristics
Write I/O Port
Halt
1
0
1
0
1
1
1
Read Memory
1 (HIGH)
Code Access
0
1
1
0
Write Memory
Passive
1
0
1
0
S
0
17/37
Semiconductor
MSM80C88A-10RS/GS/JS
RQ/GT
0
RQ/GT
1
REQUEST/GRANT:Input/Output
These lines are used for Bus Request from other devices and Bus GRANT to other devices.
These lines are bidirectional and active low.
LOCK
LOCK:Output
This line is active low.
When this line is low, other devices cannot gain control of the bus.
This line is high impedance hold acknowledge.
QS
0
/QS
1
QUEUE STATUS: Output
These are Queue Status Lines that indicate internal instruction queue status.
0
1 (HIGH)
1
First Byte of Op Code from Queue
0 (LOW)
No operation
QS
1
1
0
1
0
QS
0
Characteristics
Empty the Queue
Subsequent Byte from Queue
The following pin function descriptions are minimum mode only. Other pin functions are
already described.
IO/M
STATUS: Output
This line selects memory address space or I/O address space.
When this line is low, the CPU selects memory address space and when it is high, the CPU
selects I/O address space.
This line is high impedance during hold acknowledge.
WR
WRITE: Output
This line indicates that the CPU is in a memory or I/O write cycle.
This line is a write strobe signal when the CPU writes data to memory or an I/O device.
This line is active low. This line is high impedance during hold acknowledge.
INTA
INTERRUPT ACKNOWLEDGE: Output
This line is a read strobe signal for the interrupt acknowledge cycle.
This line is active low.
18/37
Semiconductor
MSM80C88A-10RS/GS/JS
ALE
ADDRESS LATCH ENABLE: Output
This line is used for latching an address into the MSM82C12 address latch it is a positive pulse
and the trailing edge is used to strobe the address. This line is never floated.
DT/R
DATA TRANSMIT/RECEIVE: Output
This line is used to control the direction of the bus transceiver.
When this line is high, the CPU transmits data, and when it is low. the CPU receives data.
This line is high impedance during hold acknowledge.
DEN
DATA ENABLE: Output
This line is used to control the output enable of the bus transceiver. This line is active low. This
line is high impedance during hold acknowledge.
HOLD
HOLD REQUEST: Input
This line is used for a Bus Request from an other device.
This line is active high.
HLDA
HOLD ACKNOWLEDGE: Output
This line is used for a Bus Grant to an other device.
This line is active high.
SS
0
STATUS: Output
This line is logically equivalent to S
0
in the maximum mode.
19/37
Semiconductor
MSM80C88A-10RS/GS/JS
STATIC OPERATION
The MSM80C88A-10 circuitry is of static design. Internal registers, counters and latches are
static and require no refresh as with dynamic circuit design. This eliminates the minimum
operating frequency restriction placed on other microprocessors. The MSM80C88A-10 can
operate from DC to the appropriate upper frequency limit. The processor clock may be stopped
in either state (high/low) and held there indefinitely. This type of operation is especially useful
for system debug or power critical applications.
The MSM80C88A-10 can be signal stepped using only the CPU clock. This state can be
maintained as long as is necessary. Signal step clock operation allows simple interface circuitry
to provide critical information for bringing up your system.
Static design also allows very low frequency operation (down to DC). In a power critical
situation, this can provide extremely low power operation since 80C88A power dissipation is
directly related to operating frequency. As the system frequency is reduced, so is the operating
power until, ultimately, at a DC input frequency, the MSM80C88A-10 power requirement is the
standby current (500 mA maximum).
FUNCTIONAL DESCRIPTION
General Operation
The internal function of the MSM80C88A-10 consists of a Bus interface Unit (BIU) and an
Execution Unit (EU). These units operate mutually but perform as separate processors.
The BIU performs instruction fetch and queueing, operand fetch, DATA read and write address
relocation and basic bus control. By performing instruction prefetch while waiting for decoding
and execution of instruction, the CPU's performance is increased. Up to 4-bytes for instruction
stream can be queued.
EU receives pre-fetched instructions from the BIU queue, decodes and executes instructions
and provides an un-relocated operand address to the BIU.
Memory Organization
The MSM80C88A-10 has a 20-bit address to memory. Each address has 8-bit data width.
Memory is organized 00000H to FFFFFH and is logically divided into four segments: code, data,
extra data and stack segment. Each segment contains up to 64 Kbytes and locates on a 16-byte
boundary. (Fig. 3a)
All memory references are made relative to a segment register according to a select rule.
Memory location FFFF0H is the start address after reset, and 00000H through 003FFH are
reserved as an interrupt pointer. There are 256 types of interrupt pointer:
Each interrupt type has a 4-byte pointer element consisting of a 16-bit segment address and a
16-bit offset address.
20/37
Semiconductor
MSM80C88A-10RS/GS/JS
Memory Organization
Reserved Memory Locations
CS
SS
DS
ES
Segment
Register File
XXXXOH
Code Segment
Stack Segment
Data Segment
Extra Data Segment
FFFFFH
OOOOOH
+Offset
64KB
Reset Bootstrap
Program Jump
FFFFFH
FFFFOH
3FFH
3FCH
7H
4H
3H
0H
Interrupt Pointer
for Type 1
Interrupt Pointer
for Type 0
Interrupt Pointer
for Type 255
Minimum and Maximum Modes
The MSM80C88A-10 has two system modes: minimum and maximum. When using the
maximum mode, it is easy to organize a multiple-CPU system with the MSM82C88-2 Bus
Controller which generates the bus control signal.
When using the minimum mode, it is easy to organize a simple system by generating the bus
control signal itself. MN/MX is the mode select pin. Definition of 24-31, 34 pin changes depends
on the MN/MX pin.
Stack
All stack pushes and pops. Memory references
relative to BP base register except data references.
Data references when relative to stack, destination
of string operation, or explicitly overridden.
Local Data
External (Global Data)
Destination of string operations: Explicitly
selected using a segment override.
STACK (CS)
Instructions
Automatic with all instruction prefetch.
CODE (CS)
Memory Reference Need
Segment Selection Rule
Segment Register Used
DATA (DS)
EXTRA (ES)
21/37
Semiconductor
MSM80C88A-10RS/GS/JS
Bus Operation
The MSM80C88A-10 has a time multiplexed address and data bus. If a non-multiplexed bus is
desired for the system, it is only needed to add the address latch.
A CPU bus cycle consists of at least four clock cycles: T
1
, T
2
, T
3
and T
4
. (Fig. 4)
The address output occurs during T
1
, and data transfer occurs during T
3
and T
4
. T
2
is used for
changing the direction of the bus during read operation. When the device which is accessed by
the CPU is not ready to data transfer and send to the CPU "NOT READY" is indicated T
W
cycles
are inserted between T
3
and T
4
.
When a bus cycle is not needed, T
1
cycles are inserted between the bus cycles for internal
execution. At the T
1
cycle an ALE signal is output from the CPU or the MSM82C88-2 depending
in MN/MX, at the trailing edge of an ALE, a valid address may be latched. Status bits S
0
, S
1
and
S
2
are used, in maximum mode, by the bus controller to recognize the type of bus operation
according to the following table.
Status bits S
3
through S
6
are multiplexed with A
16
-A
19
, and therefore they are valid during T
2
through T
4
. S
3
and S
4
indicate which segment register was selected on the bus cycle, according
to the following table.
0
0
0
Read I/O
0 (LOW)
Interrupt acknowledge
S
2
0
1
1
0
S
1
Characteristics
Write I/O
Halt
1
0
1
0
1
1
1
Read Data from Memory
1 (HIGH)
Instruciton Fetch
0
1
1
0
Write Data to Memory
Passive (no bus cycle)
1
0
1
0
S
0
S
5
indicates interrupt enable Flag.
I/O Addressing
The MSM80C88A-10 has a 64 Kbyte I/O. When the CPU accesses an I/O device, addresses A
0
-
A
15
are in same format as a memory access, and A
16
-A
19
are low.
I/O ports addresses are same as four memory.
0
1 (HIGH)
1
Stack
0 (LOW)
Alternate Data (Extra Segment)
S
4
1
0
1
0
S
3
Characteristics
Code or None
Data
22/37
Semiconductor
MSM80C88A-10RS/GS/JS
Basic System Timing
T
1
T
2
T
3
T
TWAIT
T
4
T
1
T
2
T
3
T
WAIT
T
4
(4 + N*WAIT) = T
CY
(4 + N*WAIT) = T
CY
Goes inactive in the state
just prior to T
4
A
19
- A
16
A
19
- A
16
S
6
- S
3
S
6
- S
3
A
15
- A
8
A
15
- A
8
A
7
- A
0
D
7
- D
0
Bus reserved
for Data In
Valid
A
7
- A
0
Data Out (D
7
- D
0
)
Ready
Ready
Wait
Wait
Memory Access Time
CLK
ALE
S
2
, S
1
, S
0
ADDR/
Status
RD, INTA
ADDR/
Data
ADDR
Ready
DT/R
DEN
WR
23/37
Semiconductor
MSM80C88A-10RS/GS/JS
EXTERNAL INTERFACE
Reset
CPU initialization is executed by the RESET pin. The MSM80C88A-10's RESET High signal is
required for greater than 4 clock cycles.
The rising edge of RESET terminates the present operation immediately. The falling edge of
RESET triggers an internal reset sequence for approximately 10 clock cycles. After internal reset
sequence is finished, normal operation begins from absolute location FFFF0H.
Interrupt Operations
The interrupt operation is classified as software or hardware, and hardware interrupt is
classified as non-markable or maskable.
An interrupt causes a new program location which is defined by the interrupt pointer table,
according to the interrupt type. Absolute location 00000H through 003FFH is reserved for the
interrupt pointer table. The interrupt pointer table consists of 256-elements. Each element is 4
bytes in size and corresponds to an 8-bit type number which is sent from an interrupt request
device during the interrupt acknowledge cycle.
Non-maskable Interrupt (NMI)
The MSM80C88A-10 has a non-maskable interrupt (NMI) which is of higher priority than a
maskable interrupt request (INTR).
An NMI request pulse width needs minimum of 2 clock cycles. The NMI will be serviced at the
end of the current instruction or between string manipulations.
Maskable Interrupt (INTR)
The MSM80C88A-10 provides another interrupt request (INTR) which can be masked by
software. INTR is level triggerd, so it must be held until interrupt request is acknowledged.
The INTR will be serviced at the end of the current instruction or between string manipulations.
Interrupt Acknowledge
During the interrupt acknowledge sequence, further interrupts are disabled. The interrupt
enable bit is reset by any interrupt, after which the Flag register is automatically pushed onto
the stack. During an acknowledge sequence, the CPU emits the lock signal from T
2
of first bus
cycle to T
2
of second bus cycle. At the second bus cycle, a byte is fetched from the external device
as a vector which identifies the type of interrupt. This vector is multiplied by four and used as
an interrupt pointer address (INTR only).
The interrupt Return (IRET) instruction includes a Flag pop operation which returns the
original interrupt enable bit when it restores the Flag.
24/37
Semiconductor
MSM80C88A-10RS/GS/JS
HALT
When a Halt instruction is executed, the CPU enters Halt state. An interrupt request or RESET
will force the MSM80C88A-10 out of the Halt state.
System Timing Minimum Mode
A bus cycle begins at T
1
with an ALE signal. The trailing edge of ALE is used to latch the address.
From T
1
to T
4
the IO/M signal indicates a memory or I/O operation. From T
2
to T
4
, the address
data bus changes the address but to the data bus.
The read (RD), write (WR), and interrupt acknowledge (INTA) signals caused the addressed
device to enable the data bus. These signals become active at the beginning of T
2
and inactive
at the beginning of T
4
.
System Timing Maximum Mode
In maximum mode, the MSM82C88-2 Bus Controller is added to system. The CPU sends status
information to the Bus Controller. Bus timing signals are generated by the Bus Controller. Bus
timing is almost the same as in minimum mode.
Interrupt Acknowledge Sequence
ALE
LOCK
INTA
AD
0
-
AD
7
T
1
T
2
T
3
T
4
T
I
T
1
T
2
T
3
T
4
Type Vector
Float
25/37
Semiconductor
MSM80C88A-10RS/GS/JS
BUS HOLD CIRCUITRY
To avoid high current conditions caused by floating inputs to CMOS devices, and to eliminate
the need for pull-up/down resistors, "bus-hold" circuitry has been used on MSM80C88A-10
pins 2-16, 26-32, and 34-39 (Figures 6a, 6b). These circuits will maintain the last valid logic state
if no driving source is present (i.e. an unconnected pin or a driving source which goes to a high
impedance state). To overdrive the "bus hold" circuits, an external driver must be capable of
supplying approximately 400 mA minimum sink or source current at valid input voltage levels.
Since this "bus hold" circuitry is active and not a "resistive" type element, the associated power
supply current is negligible and power dissipation is significantly reduced when compared to
the use of passive pull-up resistors.
Input Buffer exists only on I/O pins
"Pull-Up/Pull-Down"
Input
Protection
Circuitry
Input
Buffer
Output
Driver
Bond
Pad
External
Pin
Figure 6a. Bus Hold Circuitry Pin 2-16, 35-39
Input Buffer exists only on I/O pins
P
CC
Input
Protection
Circuitry
Input
Buffer
Output
Driver
Bond
Pad
External
Pin
"Pull-Up"
P
Figure 6b. Bus Hold Circuit Pin 26-32, 34
26/37
Semiconductor
MSM80C88A-10RS/GS/JS
MOV = Move:
Register/memory to/from register
Immediate to register/memory
Immediatye to register
Memory to accumulator
Accumulator to memory
Register/memory to segment register
Segment register to register/memory
7
1
1
1
1
1
1
1
6
0
1
0
0
0
0
0
5
0
0
1
1
1
0
0
4
0
0
1
0
0
0
0
3
1
0
w
0
0
1
1
2
0
1
0
0
1
1
1
d
1
reg
0
1
1
0
0
w
w
w
w
0
0
7
mod
mod
mod
mod
6
5
0
0
0
4
reg
0
data
addr-low
addr-low
reg
reg
3
0
2
1
r/m
r/m
r/m
r/m
0
7
6
5
4
data
data if w = 1
addr-high
addr-high
3
2
1
0
7
6
5
4
data if w = 1
3
2
1
0
PUSH = Push:
Register/memory
Register
Segment register
1
0
0
1
1
0
1
0
0
1
1
reg
1
0
1
1
1
reg
1
1
0
mod
1
1
0
r/m
POP = Pop:
Register/memory
Register
Segment register
1
0
0
0
1
0
0
0
0
0
1
reg
1
1
1
1
1
reg
1
1
1
mod
0
0
0
r/m
XCHG = Exchange:
Register/memory with register
Register with accumulator
1
1
0
0
0
0
0
1
0
0
1
1
reg
w mod
reg r/m
IN = Input from:
Fixed port
Variable port
1
1
1
1
1
1
0
0
0
1
1
1
0
0
w
w
port
OUT = Output to:
Fixed port
Variable port
XLAT = Translate byte to AL
LEA = Load EA to register
LDS = Load pointer to DS
LES = Load pointer to ES
LAHF = Load AH with flags
SAHF = Store AH into flags
PUSHF = Push flags
POPF = Pop flags
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
w
w
1
1
1
0
1
0
0
1
mod
mod
mod
reg
reg
reg
r/m
r/m
r/m
port
DATA TRANSFER
27/37
Semiconductor
MSM80C88A-10RS/GS/JS
ADD = Add:
Reg./memory with register to either
Immediate to register/memory
Immediate to accumulator
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
d
s
0
w
w
w
mod
mod
0
0
data
reg
0
r/m
r/m
data
data if w = 1
data if s:w = 01
ADC = Add with carry:
Reg./memory with register to either
Immediate to register/memory
Immediate to accumulator
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
d
s
0
w
w
w
mod
mod
0
1
data
reg
0
r/m
r/m
data
data if w = 1
data if s:w = 01
INC = Increment:
Register/memory
Register
AAA = ASCII adjust for add
DAA = Decimal adjust for add
1
0
0
0
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
0
1
1
1
1
reg
1
1
w
1
1
mod
0
0
0
r/m
SUB = Subtract:
Reg./memory with register to either
Immediate from register/memory
Immediate from accumulator
0
1
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
d
s
0
w
w
w
mod
mod
1
0
data
reg
1
r/m
r/m
data
data if w = 1
data if s:w = 01
SBB = Subtract with borrow:
Reg./memory and register to either
Immediate from register/memory
Immediate from accumulator
0
1
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
1
d
s
0
w
w
w
mod
mod
0
1
data
reg
1
r/m
r/m
data
data if w = 1
data if s:w = 01
DEC = Decrement:
Register/memory
Register
NEG = Change sign
1
0
1
1
1
1
1
0
1
1
0
1
1
1
0
1
1
1
reg
1
w
w
mod
mod
0
0
0
1
1
1
r/m
r/m
CMP = Compare:
Register/memory and register
Immediate with register/memory
Immediate from accumulator
AAS = ASCII adjust for subtract
0
1
0
0
0
0
0
0
1
0
1
1
1
0
1
1
1
0
1
1
0
0
1
1
d
s
0
1
w
w
w
1
mod
mod
1
1
data
reg
1
r/m
r/m
data
data if w = 1
data if s:w = 01
ARITHMETHIC
28/37
Semiconductor
MSM80C88A-10RS/GS/JS
DAS = Decimal adjust for subtract
MUL = Multiply (unsigned)
IMUL = Integer multiply (signed)
AAM = ASCII adjust for multiply
DIV = Divide (unsigned)
IDIV = Integer divide (signed)
AAD = ASCII adjust for divide
CBW = Convert byte to word
CWD = Convert word to double word
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
1
0
0
0
1
w
w
0
w
w
1
0
1
mod
mod
0
mod
mod
0
0
0
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1
0
1
1
0
0
r/m
r/m
1
r/m
r/m
1
0
0
29/37
Semiconductor
MSM80C88A-10RS/GS/JS
NOT = Invert
SHL/SAL = Shift logical/arithmetic left
SHR = Shift logical right
SAR = Shift arithmetic right
ROL = Rotate left
ROR = Rotate right
RCL = Rotate left through carry
RCR = Rotate right through carry
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
v
v
v
v
v
v
v
w
w
w
w
w
w
w
w
mod
mod
mod
mod
mod
mod
mod
mod
0
1
1
1
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
r/m
r/m
r/m
r/m
r/m
r/m
r/m
r/m
AND = And:
Reg./memory with register to either
Immediate to register/memory
Immediate to accumulator
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
d
0
0
w
w
w
mod
mod
1
0
data
reg
0
r/m
r/m
data
data if w = 1
data if w = 1
TEST = And function to flags, no result:
Register/memory and register
Immediate data and register/memory
Immediate data and accumulator
1
1
1
0
1
0
0
1
1
0
1
0
0
0
1
1
1
0
0
1
0
w
w
w
mod
mod
0
0
data
reg
0
r/m
r/m
data
data if w = 1
data if w = 1
OR = Or:
Reg./memory and register to either
Immediate to register/memory
Immediate to accumulator
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
d
0
0
w
w
w
mod
mod
0
0
data
reg
1
r/m
r/m
data
data if w = 1
data if w = 1
XOR = Exclusive or:
Reg./memory and register to either
Immediate to register/memory
Immediate to accumulator
0
1
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
d
0
0
w
w
w
mod
mod
1
1
data
reg
0
r/m
r/m
data
data if w = 1
data if w = 1
LOGIC
30/37
Semiconductor
MSM80C88A-10RS/GS/JS
CJMP = Conditional JMP
JE/JZ = Jump on equal/zero
JZ/JNGE = Jump on less/not greater or equal
JLE/JNG = Jump on less or equal/not greater
JB/JNAE = Jump on below/not above or equal
JBE/JNA = Jump on below or equal/not above
JP/JPE = Jump on parity/parity even
JO = Jump on over flow
JS = Jump on sign
JNE/JNZ = Jump on not equal/not zero
JNL/JGE = Jump on not less/greater or equal
JNLE/JG = Jump on not less or equal/greater
JNB/JAE = Jump on not below/above or equal
JNBE/JA = Jump on not below or equal/above
JNP/JPO = Jump on not parity/parity odd
JNO = Jump on not overflow
JNS = Jump on not sigh
LOOP = Loop CX times
LOOPZ/LOOPE = Loop while zero/equal
LOOPNZ/LOOPNE = Loop while not zero equal
JCXZ = Jump on CX zero
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
1
0
0
1
0
1
0
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
INT = Interrupt
Type specified
Type 3
INTO = Interrupt on overflow
IRET = Interrupt return
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
type
REP = Repeat
MOVS = Move byte/word
CMPS = Compare byte/word
SCAS = Scan byte/word
LODS = Load byte/word to AL/AX
STOS = Store byte/word from AL/AX
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
0
1
1
0
1
z
w
w
w
w
w
STRING MANIPULATION
31/37
Semiconductor
MSM80C88A-10RS/GS/JS
CLC = Clear carry
CMC = Complementary carry
STC = Set carry
CLD = Clear direction
STD = Set direction
CLI = Clear interrupt
STI = Set interrupt
HLT = Halt
WAIT = Wait
ESC = Escape ( to external device)
LOCK = Bus lock prefix
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
x
0
0
0
0
0
0
1
1
0
1
x
0
0
1
1
0
1
0
1
0
1
x
0
mod
x
x
x
r/m
PROCESSOR CONTROL
CALL = Call:
Direct within segment
Indirect within segment
Direct intersegment
Indirect intersegment
7
1
1
1
1
6
1
1
0
1
5
1
1
0
1
4
0
1
1
1
3
1
1
1
1
2
0
1
0
1
1
0
1
1
1
0
0
1
0
1
7
mod
mod
6
5
0
0
4
disp-low
1
offset-low
seg-low
1
3
0
1
2
1
r/m
r/m
0
7
6
5
4
disp-high
offset-high
seg-high
3
2
1
0
7
6
5
4
3
2
1
0
JMP = Unconditional Jump:
Direct within segment
Direct within segment-short
Indirect within segment
Direct intersegment
Indirect intersegment
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
1
1
0
0
1
0
1
0
1
1
1
1
1
1
1
0
0
mod
mod
1
1
disp-low
disp
0
offset-low
seg-low
0
0
1
r/m
r/m
disp-high
offset-high
seg-high
RET = Return from CALL:
Within segment
Within seg. adding immediate to SP
Intersegment
Intersegment adding immediate to SP
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
1
0
data-low
data-low
data-high
dat-high
CONTROL TRANSFER
32/37
Semiconductor
MSM80C88A-10RS/GS/JS
Notes: AL = 8-bit accumulator
AX = 18-bit accumulator
CX = Count register
DS = Data segment
EX = Extra segment
Above/below refers to unsigned value
Greater=more positive
Less=less positive (more negative) signed value
If d=1 then "to" reg: If d=0 then "from" reg.
If w=1 then word instruction: If w=0 then byte instruction
If mod=11 then r/m is treated as a REG field
If mod=00 then DISP=0*, disp-low and disp-high are absent
If mod=01 then DISP=disp-low sign-extended to 16 bits, disp-high is absent
If mod=10 then DISP=disp-high: disp-low
If r/m=000 then EA=(BX)+(SI)+DISP
If r/m=001 then EA=(BX)+(DI)+DISP
If r/m=010 then EA=(BP)+(SI)+DISP
If r/m=011 then EA=(BP)+(DI)+DISP
If r/m=100 then EA=(SI)+DISP
If r/m=101 then EA=(DI)+DISP
If r/m=110 then EA=(BP)+DISP*
If r/m=111 then EA=(BX)+DISP
DISP follows 2nd byte of instruction (before data if required)
* except if mod=00 and r/m=110 then EA-disp-high: disp-low
If s:w=01 then 16 bits of immediate data form the operand
If s:w=11 then an immediate data byte is sign extended to form the 16-bit operand
If v=0 then "count"=1:if v=1 then "count" in (CL)
x=don' t care
z is used for string primitives for comparison with ZF FLAG
SEGMENT OVERRIDE PREFIX
001 reg 110
REG is assigned according to the following table:
16-Bit (w=1)
8-Bit
(w=0)
Segment
000
AX
000
AL
00
ES
001
CX
001
CL
01
CS
010
DX
010
DL
10
SS
011
BX
011
BL
11
DS
100
SP
100
AH
101
BP
101
CH
110
SI
110
DH
111
DI
111
BH
Instructions which reference the flag register file as a 16-bit object use the symbol
FLAGS to represent the file:
FLAGS=x:x:x:x:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
33/37
Semiconductor
MSM80C88A-10RS/GS/JS
NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES
The conventional low speed devices are replaced by high-speed devices as shown below.
When you want to replace your low speed devices with high-speed devices, read the replacement
notice given on the next pages.
High-speed device (New)
Low-speed device (Old)
Remarks
M80C85AH
M80C85A/M80C85A-2
8bit MPU
M80C86A-10
M80C86A/M80C86A-2
16bit MPU
M80C88A-10
M80C88A/M80C88A-2
8bit MPU
M82C84A-2
M82C84A/M82C84A-5
Clock generator
M81C55-5
M81C55
RAM.I/O, timer
M82C37B-5
M82C37A/M82C37A-5
DMA controller
M82C51A-2
M82C51A
USART
M82C53-2
M82C53-5
Timer
M82C55A-2
M82C55A-5
PPI
34/37
Semiconductor
MSM80C88A-10RS/GS/JS
Differences between MSM80C88A-10 and MSM80C88A-2, MSM80C88A
1) Manufacturing Process
All devices use a 1.5 m Si-CMOS process technology.
2) Design
Although circuit timings of these devices are a little different, these devices have the same chip size
and logics.
3) Electrical Characteristics
Oki's '96 Data Book for MICROCONTROLLER describes that the MSM80C88A-10 satisfies the
electrical characteristics of the MSM80C88A-2 and MSM80C88A.
4) Other notices
1) The noise characteristics of the high-speed MSM80C88A-10 (for 10 MHz) are a little different from
those of the MSM80C88A-2 and MSM80C88A. Therefore when devices are replaced for upgrading,
it is recommended to perform noise evaluation.
2) The characteristics of the MSM80C88A-10 basically satisfy those of the MSM80C88A-2 and
MSM80C88A but their timings are a little different. When critical timing is required in designing
it is recommended to evaluate operating margins at various temperatures and voltages.
35/37
Semiconductor
MSM80C88A-10RS/GS/JS
(Unit : mm)
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
DIP40-P-600-2.54
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
6.10 TYP.
36/37
Semiconductor
MSM80C88A-10RS/GS/JS
(Unit : mm)
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
QFJ44-P-S650-1.27
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
2.00 TYP.
Mirror finish
37/37
Semiconductor
MSM80C88A-10RS/GS/JS
(Unit : mm)
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
QFP56-P-1519-1.00-K
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.46 TYP.
Mirror finish
PDF 
ZIP