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¡ Semiconductor

MSM82C53-2RS/GS/JS

¡ Semiconductor

MSM82C53-2RS/GS/JS

CMOS PROGRAMMABLE INTERVAL TIMER

E2O0018-27-X2

GENERAL DESCRIPTION

The MSM82C53-2RS/GS/JS is programmable universal timers designed for use in
microcomputer systems. Based on silicon gate CMOS technology, it requires a standby current
of only 100 mA (max.) when the chip is in the nonselected state. During timer operation, power
consumption is still very low only 8 mA (max.) at 8 MHz of current required.
The device consists of three independent counters, and can count up to a maximum of 8 MHz
(MSM82C53-2). The timer features six different counter modes, and binary count/BCD count
functions. Count values can be set in byte or word units, and all functions are freely
programmable.

FEATURES

· Maximum operating frequency of 8 MHz (MSM82C53-2)
· High speed and low power consumption achieved through silicon gate CMOS technology
· Completely static operation
· Three independent 16-bit down-counters
· 3 V to 6 V single power supply
· Six counter modes available for each counter
· Binary and decimal counting possible
· 24-pin Plastic DIP (DIP24-P-600-2.54): (Product name: MSM82C53-2RS)
· 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C53-2JS)
· 32-pin Plastic SSOP(SSOP32-P-430-1.00-K): (Product name: MSM82C53-2GS-K)

This version: Jan. 1998

Previous version: Aug. 1996

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MSM82C53-2RS/GS/JS

PIN CONFIGURATION (TOP VIEW)

24 pin Plastic DIP

32 pin Plastic SSOP

CLK

OUT

GATE

GND

Vcc
WR
RD
NC
CS
A

CLK

OUT

GATE

CLK

GATE

OUT

Vcc
WR

CLK

OUT

GATE

CLK

GATE

OUT

CLK

OUT

GATE

GND

CLK

OUT

GATE

CLK

OUT0

GATE0

GND

OUT

GATE

CLK

28 pin Plastic QFJ

(NC denotes "not connected")

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MSM82C53-2RS/GS/JS

ABSOLUTE MAXIMUM RATINGS

55 to + 150

MSM82C53-2RS

Supply Voltage

0.5 to + 7

Input Voltage

0.5 to V

+ 0.5

Output Voltage

OUT

0.5 to V

+ 0.5

Storage Temperature

STG

°C

Power Dissipation

0.7

Parameter

Units

Symbol

Respect

to GND

Ta = 25°C

Condition

Rating

MSM82C53-2GS

MSM82C53-2JS

0.9

OPERATING RANGES

RECOMMENDED OPERATING CONDITIONS

DC CHARACTERISTICS

Typ.

Max.

"L" Output Voltage

0.45

"H" Output Voltage

Parameter

Unit

Symbol

Min.

3.7

= 4 mA

= 1 mA

Condition

= 4.5 V to 5.5 V

= 40°C to +85°C

Input Leak Current

Output Leak Current

0 £ V

£ V

0 £ V

OUT

£ V

CS V

- 0.2 V

0.2 V

Standby Supply
Current

Operating Supply
Current

CCS

100

CLK

= 125 ns

= 0 pF

Condition

Supply Voltage

= 0.2 V, V

= V

-0.2 V,

Operating Frequency 2.6 MHz

Operating Temperature

Range

3 to 6

40 to +85

°C

Parameter

Unit

Symbol

Typ.

Supply Voltage

+25

"L" Input Voltage

"H" Input Voltage

Min.

4.5

0.3

2.2

Max.

5.5

+85

+0.8

+ 0.3

Parameter

Unit

Symbol

°C

Operating Temperature

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MSM82C53-2RS/GS/JS

AC CHARACTERISTICS

Note: Timing measured at V

= 0.8 V and V

= 2.2 V for both inputs and outputs.

Parameter

Symbol

Unit

Condition

Max.

Min.

MSM82C53-2

Address Set-up Time before Reading

= 4.5 V to 5.5 V, Ta = 40 to +85°C)

Address Hold Time after Reading

Read

Cycle

Read Recovery Time

Read Pulse Width

150

Address Set-up Time before Writing

RVR

200

Address Hold Time after Writing

Write Pulse Width

Data Input Set-up Time before Writing

Write
Cycle

150

Data Input Hold Time after Writing

100

Write Recovery Time

RVW

Clock Cycle Time

CLK

200

Clock "H" Pulse Width

PWH

125

D.C.

Clock "L" Pusle Width

PWL

Clock

and

Gate

Timing

"H" Gate Pulse Width

= 150 pF

"L" Gate PUlse Width

Gate Input Hold Time after Clock

Gate Input Set-up Time before Clock

Output Delay Time after Reading

120

Output Delay Time after Gate

ODG

Output Delay Time after Clock

120

Output Delay Time after Address

150

180

Output Floating Delay Time after
Reading

Delay

Time

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MSM82C53-2RS/GS/JS

DESCRIPTION OF PIN FUNCTIONS

SYSTEM INTERFACING

16 bits

Address Bus

Control Bus

8 bits

Data Bus

MSM82C53-2

OUT GATE CLK

Counter #0

OUT GATE CLK

Counter #1

OUT GATE CLK

Counter #2

Pin Symbol

Function

Name

- D

Three-state 8-bit bidirectional data bus used when writing control words
and count values, and reading count values upon reception of WR and
RD signals from CPU.

Bidirectional

Data Bus

Input/Output

- A

One of the three internal counters or the control word register is selected
by A

combination. These two pins are normally connected to the two

lower order bits of the address bus.

Address Input

Input

Data can be transferred from MSM82C53-2 to CPU when this pin is at low
level.

Read Input

Input

Data can be transferred from CPU to MSM82C53-2 when this pin is at low
level.

Write Input

Input

CLK

Supply of three clock signals to the three counters incorporated in
MSM82C53-2.

Clock Input

Input

GATE

Control of starting, interruption, and restarting of counting in the three
respective counters in accordance with the set control word contents.

Gate Input

Input

OUT

Output of counter output waveform in accordance with the set mode and
count value.

Counter Output

Output

Data transfer with the CPU is enabled when this pin is at low level. When
at high level, the data bus (D

thru D

) is switched to high impedance

state where neither writing nor reading can be executed. Internal registers,
however, remain unchanged.

Chip Select

Input

Input/Output

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MSM82C53-2RS/GS/JS

DESCRIPTION OF BASIC OPERATIONS

Data transfers between the internal registers and the external data bus is outlined in the
following table.

Function

Data Bus to Counter #0 Writing

Data Bus to Counter #1 Writing

Data Bus to Counter #2 Writing

Data Bus to Control Word Register Writing

Data Bus from Counter #0 Reading

Data Bus from Counter #1 Reading

Data Bus from Counter #2 Reading

Data Bus High Impedance Status

¥ denotes "not specified".

DESCRIPTION OF OPERATION

MSM82C53-2 functions are selected by a control word from the CPU. In the required program
sequence, the control word setting is followed by the count value setting and execution of the
desired timer operation.

Control Word and Count Value Program

Each counter operation mode is set by control word programming. The control word format
is out-lined below.

SC1

SC0

RL1

RL0

BCD

Select Counter

Read/Load

Mode

BCD

(CS=0, A

, A

=1, 1, RD=1, WR=0)

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MSM82C53-2RS/GS/JS

· Select Counter (SC0, SC1):

Selection of set counter

· Read/Load (RL1, RL0):

Count value Reading/Loading format setting

· Mode (M2, M1, M0):

Operation waveform mode setting

Set Contents

Mode 0 (Interrupt on Terminal Count)

Mode 1 (Programmable One-Shot)

Mode 2 (Rate Generator)

Mode 3 (Square Wave Generator)

Mode 4 (Software Triggered Strobe)

Mode 5 (Hardware Triggered Strobe)

¥ denotes "not specified".

· BCD:

Operation count mode setting

BCD

Binary Count (16-bit Binary)

BCD Count (4-decade Binary Coded Decimal)

Set Contents

After setting Read/Load, Mode, and BCD in each counter as outlined above, next set the desired
count value. (In some Modes, counting is started immediately after the count value has been
written). This count value setting must conform with the Read/Load format set in advance.
Note that the internal counters are reset to 0000H during control word setting. The counter
value (0000H) can't be read.
If the two bytes (LSB and MSB) are written at this stage (RL0 and RL1 = 1,1), take note of the
following precaution.
Although the count values may be set in the three counters in any sequence after the control
word has been set in each counter, count values must be set consecutively in the LSB - MSB order
in any one counter.

SC1

SC0

Counter #0 Selection

Counter #1 Selection

Counter #2 Selection

Illegal Combination

Set Contents

RL1

Set Contents

RL0

Counter Latch Operation

Reading/Loading of Least Significant Byte (LSB)

Reading/Loading of Most Significant Byte (MSB)

Reading/Loading of LSB Followed by MSB

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MSM82C53-2RS/GS/JS

· Example of control word and count value setting

Counter #0: Read/Load LSB only, Mode 3, Binary count, count value 3H

Counter #1: Read/Load MSB only, Mode 5, Binary count, count value AA00H

Counter #2: Read/Load LSB and MSB, Mode 0, BCD count, count value 1234

MVI A, 1EH
OUT n3

Counter #0 control word setting

MVI A, 6AH
OUT n3

Counter #1 control word setting

MVI A, B1H
OUT n3

Counter #2 control word setting

MVI A, 03H
OUT n0

Counter #0 control value setting

MVI A, AAH
OUT n1

Counter #1 control value setting

MVI A, 34H
OUT n2

Counter #2 count value setting (LSB then MSB)

MVI A, 12H
OUT n2

Notes: n0: Counter #0 address

n1: Counter #1 address
n2: Counter #2 address
n3: Control word register address

Mode

Remarks

MIn.

Max,

0 executes 10000H count (ditto in other modes)

1 cannot be counted

1 executes 10001H count

· The minimum and maximum count values which can be counted in each mode are listed

below.

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MSM82C53-2RS/GS/JS

Mode Definition

· Mode 0 (terminal count)

The counter output is set to "L" level by the mode setting. If the count value is then written
in the counter with the gate input at "H" level (that is, upon completion of writing the MSB
when there are two bytes), the clock input counting is started. When the terminal count is
reached, the output is switched to "H" level and is maintained in this status until the control
word and count value are set again.
Counting is interrupted if the gate input is switched to "L" level, and restarted when switched
back to "H" level.
When Count Values are written during counting, the operation is as follows:

1-byte Read/Load. ............ When the new count value is written, counting is stopped

immediately, and then restarted at the new count value by the next
clock.

2-byte Read/Load ............. When byte 1 (LSB) of the new count value is written, counting is

stopped immediately. Counting is restarted at the new count
value when byte 2 (MSB) is written.

· Mode 1 (programmable one-shot)

The counter output is switched to "H" level by the mode setting. Note that in this mode,
counting is not started if only the count value is written. Since counting has to be started in
this mode by using the leading edge of the gate input as a trigger, the counter output is
switched to "L" level by the next clock after the gate input trigger. This "L" level status is
maintained during the set count value, and is switched back to "H" level when the terminal
count is reached.
Once counting has been started, there is no interruption until the terminal count is reached,
even if the gate input is switched to "L" level in the meantime. And although counting
continues even if a new count value is written during the counting, counting is started at the
new count value if another trigger is applied by the gate input.

· Mode 2 (rate generator)

The counter output is switched to "H" level by the mode setting. When the gate input is at
"H" level, counting is started by the next clock after the count value has been written. And
if the gate input is at "L" level, counting is started by using the rising edge of the gate input
as a trigger after the count value has been set.
An "L" level output pulse appears at the counter output during a single clock duration once
every n clock inputs where n is the set count value. If a new count value is written during
while counting is in progress, counting is started at the new count value following output of
the pulse currently being counted. And if the gate input is switched to "L" level during
counting, the counter output is forced to switch to "H" level, the counting being restarted by
the rising edge of the gate input.

· Mode 3 (square waveform rate generator)

The counter output is switched to "H" level by the mode setting. Counting is started in the
same way as described for mode 2 above.
The repeated square wave output appearing at the counter output contains half the number
of counts as the set count value. If the set count value (n) is an odd number, the repeated square
wave output consists of only (n+1)/2 clock inputs at "H" level and (n-1)/2 clock inputs at "L"
level.
If a new count value is written during counting, the new count value is reflected immediately
after the change ("H" to "L" or "L" to "H") in the next counter output to be executed. The
counting operation at the gate input is done the same as in mode 2.

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MSM82C53-2RS/GS/JS

· Mode 4 (software trigger strobe)

The counter output is switched to "H" level by the mode setting. Counting is started in the
same way as described for mode 0. A single "L" pulse equivalent to one clock width is
generated at the counter output when the terminal count is reached.
This mode differs from 2 in that the "L" level output appears one clock earlier in mode 2, and
that pulses are not repeated in mode 4. Counting is stopped when the gate input is switched
to "L" level, and restarted from the set count value when switched back to "H" level.

· Mode 5 (hardware trigger strobe)

The counter output is switched to "H" level by the mode setting. Counting is started, and the
gate input used, in the same way as in mode 1.
The counter output is identical to the mode 4 output.
The various roles of the gate input signals in the above modes are summarized in the following
table.

"H" Level

"L" Level Falling Edge

Rising Edge

Mode

Gate

Counting not possible

Counting possible

(1)
(2)

Start of counting
Retriggering

(1)
(2)

Counting not possible
Counter output forced to "H" level

Start of counting

Counting possible

(1)
(2)

Counting not possible
Counter output forced to "H" level

Start of counting

Counting possible

Counting not possible

Counting possible

(1)
(2)

Start of counting
Retriggering

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MSM82C53-2RS/GS/JS

(n = 4)

(n = 2)

(GATE="H")

(n = 4)

CLK

OUT

GATE

OUT

Mode 0

Mode 1

(n = 4)

CLK

GATE

OUT

GATE

OUT

(n = 4)

(n = 2)

(GATE="H")

(n = 4)

Mode 2

CLK

OUT

GATE

OUT

(n = 4)

(n = 3)

(GATE="H")

(n = 5)

Mode 3

CLK

OUT

GATE

OUT

CLK

OUT

GATE

OUT

Mode 4

(GATE="H")

CLK

GATE

OUT

GATE

OUT

Mode 5

(n = 4)

Note: "n" is the value set in the counter.

Figures in these diagrams refer to counter values.

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MSM82C53-2RS/GS/JS

Reading of Counter Values

All MSM82C53-2 counting is down-counting, the counting being in steps of 2 in mode 3.
Counter values can be read during counting by (1) direct reading, and (2) counter latching
("read on the fly").

· Direct reading

Counter values can be read by direct reading operations.
Since the counter value read according to the timing of the RD and CLK signals is not
guaranteed, it is necessary to stop the counting by a gate input signal, or to interrupt the clock
input temporarily by an external circuit to ensure that the counter value is correctly read.

· Counter latching

In this method, the counter value is latched by writing counter latch command, thereby
enabling a stable value to be read without effecting the counting in any way at all. An example
of a counter latching program is given below.
Counter latching executed for counter #1 (Read/Load 2-byte setting)

0 1 0 0 ¥ ¥ ¥ ¥

MVI A

Dentotes counter latching

OUT n3

Write in control word address (n3)

IN n1

Reading of the LSB of the counter
value latched from counter #1

n1: Counter #1 address

MOV B, A
IN n1
MOV C, A

Reading of MSB from counter #1

The counter value at this point is latched.

MSM82C53-2

CLK

OUT

CLK

OUT

CLK

OUT

Use counter #1 and counter #2

Counter #1: mode 0, upper order 16-bit counter

value

Counter #2: mode 2, lower order 16-bit counter

value

This setting enables counting up to a maximum of 2

Example of Practical Application
· MSM82C53-2 used as a 32-bit counter.

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MSM82C53-2RS/GS/JS

NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES

The conventional low speed devices are replaced by high-speed devices as shown below.
When you want to replace your low speed devices with high-speed devices, read the replacement
notice given on the next pages.

High-speed device (New)

Low-speed device (Old)

Remarks

M80C85AH

M80C85A/M80C85A-2

8bit MPU

M80C86A-10

M80C86A/M80C86A-2

16bit MPU

M80C88A-10

M80C88A/M80C88A-2

8bit MPU

M82C84A-2

M82C84A/M82C84A-5

Clock generator

M81C55-5

M81C55

RAM.I/O, timer

M82C37B-5

M82C37A/M82C37A-5

DMA controller

M82C51A-2

M82C51A

USART

M82C53-2

M82C53-5

Timer

M82C55A-2

M82C55A-5

PPI

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MSM82C53-2RS/GS/JS

Differences between MSM82C53-5 and MSM82C53-2

1) Manufacturing Process
These devices use a 3 m Si-Gate CMOS process technology and have the same chip size.

2) Function
These devices have the same logics except for changes in AC characteristics listed in (3-2).

3) Electrical Characteristics
3-1) DC Characteristics

As shown above, the characteristics of these devices are identical under the same test condition. The

MSM82C53-2 satisfies the characteristics of the MSM82C53-5.

3-2) AC Characteristics

As shown above, the MSM82C53-2 satisfies the characteristics of the MSM82C53-5.

Parameter

Symbol

MSM82C53-5

MSM82C53-2

Address Hold Time After Write

30 ns minimum

20 ns minimum

Data Input Hold Time After Write

30 ns minimum

20 ns minimum

Clock Cycle Time

200 ns minimum

125 ns minimum

CLK

Parameter

Symbol

MSM82C53-5

MSM82C53-2

Average Operating Current

5 mA maximum

CLK

=200 ns)

8 mA maximum

CLK

=125 ns)

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