Semiconductor Components Industries, LLC, 2002

October, 2002 - Rev. 1

Publication Order Number:

AND8079/D

AND8079/D

A Low Cost DDR Memory
Power Supply Using the
NCP1571 Synchronous Buck
Converter and a LM358
Based Linear Voltage
Regulator

Prepared by: Jim Lepkowski
Senior Application Engineer

INTRODUCTION

This application note describes a low cost power supply

circuit for a DDR (Double Data Rate) memory system. The
design is based on the NCP1570/NCP1571 low voltage
synchronous buck converter. The reference design created
to evaluate the system uses a 3.80

by 2.15

two layer printed

circuit board, optimized for a small solution size at an
economical cost.

DDR memories bring new challenges to the power supply

by requiring an efficient main power of 2.5 V (V

) and a

second voltage (V

) that accurately tracks one half of V

(i.e. 1.25 V) that is capable of both sourcing and sinking
current. In addition, a third voltage is required (V

REF

) that

also tracks V

/2. A low voltage synchronous buck

converter is used to create an 8.0 A output at 2.5 V, while the
V

and V

REF

voltages are created using a unique operational

amplifier linear regulator circuit. The demonstration circuit
is designed for low power DDR systems such as desktop
PCs, but the circuit's output power capability can be
increased with the selection of the external inductor and
capacitors for high power systems such as PC workstations.

DDR Memory Power Supply Requirements

Figure 1 shows a simplified schematic of the DDR

memory system. Voltage V

powers the memory ICs, in

addition to the buffer interface circuits. The termination
voltage V

is used for the pull-up resistors and must be able

to either sink or source current. For example, if all of the
driver circuits are at a logic high state (i.e. V

= V

2.5 V), the Vtt supply will have to sink current in order to
maintain its 1.25 V. In contrast, if all of the driver circuits are
at a logic low state (i.e. V

= V

= 0 V), the Vtt supply will

have to source current because the termination resistors will
be effectively connected to ground.

Figure 1. DDR Memory Simplified Schematic

= V

Transmitter

Receiver

REF

is equal to V

/2 instead of V

in order to save power.

The power dissipated in the resistors is equal to voltage
squared divided by the bus resistance, thus a termination
voltage of V

/2 provides a factor of four power savings.

The third voltage is used as a reference voltage to the
differential amplifier input section of the receiver ICs.

A summary of the specifications for the DDR memory

system is listed below. The transient requirements are not
defined in the industry JEDEC standards.

DDR

Voltage

Output

Voltage

Tolerance

Output Current

2.5 V

200 mV

8.0 A

(

1.25 V)

(1.250 V

37.5 mV)

2.0 A

(Sink and Source)

REF

40 mV

5.0 mA

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Many industry experts have predicted that DDR memory

will soon become the standard for desktop computers, with
notebooks shortly behind. Next generation DDR-II
generation

systems are likely to have a lower V

voltage of

1.8 V with a V

and V

REF

voltage equal to 900 mV. This

lower voltage will be required to satisfy the consumer's
requirement for more memory without a large increase in
required power.

Supply Voltage (V

)

The V

2.5 V power supply is created with the NCP1571

low voltage synchronous buck controller. The NCP1571
controller contains the required circuitry for a synchronous
N-channel MOSFET buck regulator. The V

control

method is used to achieve a fast 200 ns transient response
and an output regulation of

1.0%. The IC operates at a fixed

internal frequency of 200 kHz. In addition, the NCP1571
provides the following features: undervoltage lockout
protection, programmable soft start, power good signal with
delay and overvoltage protection. Note the NCP1570 and
NCP1571 are functionally and pin for pin equivalent. The
NCP1571's under voltage lockout operation (UVLO)
feature has been modified for applications that require a
parallel standby power supply in addition to the main power
supplied by the buck converter.

Termination Supply Voltage (V

) and Reference

Voltage (V

REF

)

The V

supply voltage is equal to one half of the Vdd

voltage, or approximately 1.25 V. Operational amplifiers
U

and U

function as voltage followers to create the V

voltage. The input to U

is created by the resistive voltage

divider formed by R

and R

and divides the 2.5 V V

supply by two to form the V

REF

reference voltage. Also, U

provides filtering to remove any of the high frequency
switching noise that is results from the synchronous buck
converter. The V

output of the circuit formed by U

and

transistors Q

and Q

tracks the voltage at the non-inverting

terminal by virtue of the voltage follower circuit
configuration. Thus, the output of voltage of the V

supply

is referenced to 50% of the 2.5 V V

supply, rather than an

absolute 1.25 V reference.

The sink and source ability of the V

supply is provided

by MOSFETs Q

and Q

which are used to extend the

current capability of the operational amplifier circuit. When
the V

supply is in the current sinking mode of operation, Q

is "OFF" and Q

is "ON". The output of U

will be at a

negative voltage (i.e. 5.0 V) to control the V

of the

P-channel MOSFET (Q

) in order to maintain the V

voltage of 1.25 V. In a similar manner, when the V

supply

is in the current sourcing mode of operation, Q

is "ON" and

is "OFF". The output of U

will reach a positive voltage

(i.e. + 4.5 V) to control the V

of the N-channel MOSFET

) in order to maintain the V

voltage of 1.25 V. Resistor

is used to isolate the output of U

from V

and the bulk

capacitor C

The slew rate of the operational amplifier and the ability

of the bulk capacitors to hold the voltage at 1.25 V under the
load conditions control the transient response of the V

control loop. Note that the bulk capacitors maintain the V

voltage at approximately 1.25 V; therefore, the operational
amplifier is only required to slew its output a relatively small
amount; therefore, the relatively slow slew rate of the
LM358 operational amplifiers is not a limiting factor in the
design.

Standby Power Operation

The demonstration PCB has the provision of providing a

low power standby mode of operation to the DDR memory
system. This mode could be used to provide a 2.5 V low
current standby voltage to the memory ICs when the main
5.0 V input power is not available. A MC33375 (U

)

300 mA low dropout voltage regulator (LDO) was chosen
for the design to provide the 2.5 V standby power. The
MC33375 has an ON/OFF enable pin and is available in a
SOT-223 package. The performance of the standby
regulator was not verified.

, a N-Channel MOSFET, serves as a diode to prevent

current flow back to the main 5.0 volt input power supply
during the standby mode. The MOSFET was chosen instead
of a Schottky diode in order to minimize the voltage drop
and power consumption of the diode.

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MTB1306

D2 PAK

TP5

TP6

TP7

TP8

TP9

TP10

5 V_Input

GND_Input

12 V_Input

V_Logic

V_5P0_STBV

-12 V_Input

C12

0.1

VTT (+1.25V, 2A)

VREF (+1.25V, 2mA)

VDDQ (+2.5V, 8A)

Q2
MTB1306
D2 PAK

NCP1571

SO-8

MTD20P03HDL

DPAK

C16

C17

VCC

GATE(H)

C1
1800

10V

C2
1800

10V

C4
0.1

C5
1800

10V
Prov.

C7
1800

6.3V
Prov.

C8
1800

6.3V

C9
0.1

C11
1800

6.3V

D1
MBRM110LT
PowerMite Prov.

C15

OUT

Q4
NTD4302
D2 PAK

TP1

TP2

TP3

TP4

Tol. = 1.0%

U2A

LM358

Micro8

ON OFF

VOUT

C24
1

C20
1800

6.3V
Prov.

10K

C21
1800

6.3V
Prov.

10K

C22
0.1

C23
1800

6.3V

C18

0.15

100

200

C19

1.25V_Ref

GND_Output

1.25V_Vtt

20k

13k

2.2

Tol = 1.0%

To = 1.0%

MTB1306

D2PAK

100pF

2.5V

0.1

V-

V+
8

47k

C13

0.01

C14
0.1

MC33375ST-2.5T3

SOT-223

U2B

LM358

C3
1800

10V

GATE(L)

Vfb

GND

PWRGD

PGDELAY

COMP

C10
1800

6.3V

GND

VIN

Figure 2. DDR Memory Reference Design

Note: The provisional components were not used in the verification of the reference design.

U3 Prov.

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Component Selection

Input Inductor

The input inductor (L

) is used to isolate the input power

supply from the switching portion of the buck regulator. L

also limits the inrush current into the bulk input capacitors
and limits the input current slew rate that results from the
transient load. The inductor blocks the ripple current and
transfers the transient current requirement to the bulk input
capacitor bank.

The design equations for L

are listed below and for

connivance an inductance of 1.0

mH is chosen. The cut-off

frequency of the second order LC filter provides adequate
attenuation for the 200 kHz switching frequency of the
NCP1571.

LIN

(dI dt)Max

5 V

2.5 V

10 A

1.25

3db

LIN CIN

5400

216 Hz

where:
L

= input inductor

= bulk input capacitor(s)

dI/dt = 10 A in 5.0

Input Capacitors

The input filter capacitors provide a charge reservoir that

minimizes the supply voltage variations due to the pulsating
current through the MOSFETs. The input capacitors are
chosen primarily to meet the ripple current rating of the
capacitors.

The design equation is listed below.

ICin(RMS)

Iout2

.5)

102

5 A

where:
D = duty cycle = V

OUT

= 2.5 V/5.0 V = 0.5

OUT

= maximum output current

The Rubycon 10 V 1800

mf capacitors have a ripple

current rating of 2.55 A. Thus only 2 of the capacitors are
needed to meet the ripple requirements; however, 3
capacitors were chosen to be conservative.

Output Inductance

The main criterion in selecting the output filter inductance

OUT

) is to provide a satisfactory response to the load

transients. The inductance affects the output voltage ripple
by limiting the rate at which the current can either increase
or decrease. The design equation used for selecting L

OUT

listed below. A 2.2

mH inductor was chosen for the design.

LOUT

(VIN

VOUT)

(5 V

2.5 V)

10 A

2.5

where:

tr = output transient load time

Output Capacitors

The output capacitors are selected to meet the desired

output ripple requirements. The key specifications for the
capacitors are their ESR (Equivalent Series Resistance) and
ESL (Equivalent Series Inductance). In order to obtain a
good transient response, a combination of low value/high
frequency ceramic capacitors and bulk electrolytic
capacitors are placed as close to the load as possible.

The voltage change during the load current transient is:

VOUT

+ D

IOUT

ESL

)

ESR

)

COUT

^ D

IOUT

ESR

Empirical data indicates that most of the output voltage

change that results from the load current transients is
determined by the capacitor ESR; therefore, the maximum
allowable ESR can be approximated from the following
equation.

ESR max

VOUT

IOUT

75 mV

10 A

7.5 m

The number of capacitors is calculated by using the

equation listed below.

Number of capacitors

ESRCAP
ESR max

19 m

7.5 m

W +

2.5

The ESR of the Rubycon 6.3 V 1800

mF capacitors is

specified at 19 m

W; therefore, 3 capacitors are used in the

design.

MOSFET Selection

The output switch MOSFETs are chosen based on the gate

charge/gate-source threshold voltage, gate capacitance, on
resistance, current rating and the thermal capacity of the
package. In this DDR design, the MOSFETs were chosen for
economical reasons and have a current and power rating that
is much better than needed for this design. In addition, the
MOSFETs selected were verified by measuring the thermal
characteristics of the devices on the PCB.

The power dissipation design equation for selecting the

MOSFETs is given below.

IMAX2

RDS(ON)

)

IMAX

VDS

)

IMAX

VDS

where:

= rise time or turn-on time of MOSFET

= fall time or turn-off time of MOSFET

= switching frequency

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Schottky Diode for Synchronous MOSFET

The efficiency of the buck converter can be improved

slightly by placing a Schottky diode (D

) in parallel with the

bottom MOSFET (Q

). The body diode of Q

is used to

conduct current during the non-overlap time when both the
top (Q

) and bottom (Q

) MOSFETs are turned OFF. But

because the non-overlap time is only approximately 50 ns
for the NCP1571's 200 kHz switching speed, the efficiency
savings will be only approximately 1.0%. The
demonstration board included a provision for D

; however,

the performance of the circuit was not testing with this
diode.

Experimental Results

The experimental results of the demonstration PCB are

shown in Figures 4 through 20. Figure 3 shows the test setup
used to create the current load transients for the V

supply

voltage. The transient current load tests for the V

and V

supply voltages were created using a Kikusui Electronic
Load Controller. Unless noted, the standard test conditions
are as listed below:

1. Ambient Temperature = 23

2. V

Current Load (I

Vdd

) = 8.0 A

3. V

Current Load (I

Vtt

) = 1.25 A source load

4. V

REF

Current Load (I

REF

) = 2.5 mA

5. 5.0 V Input Voltage = 5.00 V
6. 12 V Input Voltage = 12.00 V
7. -12 V Input Voltage = -12.00 V

Figure 3. V

Transient Load Test Setup for a 2.0 A Sink to 2.0 A Source Test

2.5 V

OUT

U2A

REF

C22

C23

DDR Circuit

2.0 A
DC Current Source

Pulsating Current Source

Pulse Width = 100 ms
Period = 200 ms
l1 = 0 A
l2 = 4.0 A
Rise Time = 50

Fall Time

= 50

Circuit

DC Current Source

Pulsating Current Source

0 A

2 .0 A

2.0 A

2.0 A Current Sink Test

Circuit

DC Current Source

Pulsating Current Source

4 A

2.0 A Current Source Test

2 .0 A

2.0 A

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1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.440

2.445

2.450

2.455

2.460

2.465

2.470

2.475

Figure 4. Output Voltage vs. V

Load

Figure 5. V

Voltage vs. V

Load

Figure 6. V

and V

ref

vs. V

Load

1.214

1.216

1.218

1.220

1.222

1.224

1.226

1.228

1.230

1.232

1.234

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

Figure 7. Output Voltage vs. Input Voltage

Figure 8. Efficiency vs. V

Load

Figure 9. Efficiency vs. Input Voltage

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.75

0.76

0.77

0.78

0.79

0.80

0.81

0.82

0.74

INPUT VOLTAGE (V)

EFFICIENCY (%)

EFFICIENCY

LOAD CURRENT (A)

EFFICIENCY (%)

INPUT VOLTAGE (V)

VOL

AGE OUTPUT (V)

LOAD (A)

EFFICIENCY

VOL

AGE (V) V

& V

ref

LOAD (A)

OUTPUT VOL

AGE (V)

LOAD (A)

VOL

AGE (V)

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

ref

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Figure 20. Switching Noise Reflected to the 5.0 V Input Power Supply with a Transient Load I

Vdd

= 0 to 8.0 A,

Vtt

= 0 to 4.0 A Sourcing (i.e. 2.0 A Sinking to +2.0 A Sourcing Transient Current Load) and V

REF

= 2.45 mA

Channel 1: 5.0 V Input Voltage
Channel 2: Transient current load of I

Vdd

= 0 to 8.0 A

Table 1: Component temperature measured in still air at an

ambient temperature of 23

_C. The load conditions were:

1. V

Transient current load I

Vdd

= 0 to 8.0 A

2. V

Transient current load I

Vtt

= 0 to 4.0 A

sourcing (i.e. 2.0 A sinking to +2.0 A sourcing
transient current load)

3. Steady state V

REF

current load I

REF

= 2.5 mA

Table 1.

Circuit

Component

Temperature (

FET Diode (Q

)

41.6

Top FET (Q

)

54.2

Bottom FET (Q

)

56.4

Input Inductor (L

)

42.1

Output Inductor (L

)

57.9

Input Capacitor (C

)

33.0

Output Capacitor (C

)

31.2

NCP1571 (U

)

55.0

LM358 (U

)

46.2

Top FET (Q

)

42.1

Bottom FET (Q

)

49.3

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Table 2. Demonstration Board Bill of Materials

Item

Quantity

Reference

Part

Part No.

Package

Mfg.

Comments

C1, C2, C3,
C5

1800

F, 10 V

MBZ Series

see data sheet

Rubycon

C5 is provisional

C7, C8, C10,
C11, C20,
C21, C23

1800

F, 6.3 V

MBZ Series

see data sheet

Rubycon

C7, C20 and C21
are provisional

C4, C9, C12,
C14, C16,
C17, C22

0.1

SMT 1206

100 pF

SMT O805

C18

0.15

SMT 1206

C13

0.01

SMT O805

C15

1.0

SMT O805

C19

2.0

SMT O805

1.0

DO3316P-102HC

see data sheet

Coilcraft

2.2

DO5022P-222HC

see data sheet

Coilcraft

Q1, Q2, Q3

N-Channel

Mosfet

MTB1306

D2PAK

Semiconductor

N-Channel

Mosfet

NTD4302

DPAK Bent

Lead

Semiconductor

P-Channel

Mosfet

MTD20P03HDL

DPAK Bent

Lead

Semiconductor

10 ohm

SMT O805

47 Kohm

SMT O805

20 Kohm

SMT O805

13 Kohm

SMT O805

R5, R6

10 Kohm

SMT O805

1.0 Kohm

SMT O805

200 ohm

SMT O805

100 ohm

SMT O805

Sync. Buck

Controller

NCP1571

SO-8

Semiconductor

Op-Amp

LM358DMR2

Micro-8

Semiconductor

LDO

Regulator

MC33375ST-2.5T3

SOT-223

Semiconductor

U3 is provisional

Schottky

Diode

MBRM110LT

PowerMite

Semiconductor

D1 is provisional

NOTE:

The provisional components were not used in the verification of the reference design.

Acknowledgement

The author would like to acknowledge Tod Schiff's

assistance in designing the linear V

circuit.

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