Semiconductor Components Industries, LLC, 2002
January, 2002 Rev. 0
1
Publication Order Number:
MC100E256/D
MC100E256
5V ECL 3 Bit 4:1 Mux Latch
The MC100E256 contains three 4:1 multiplexers followed by
transparent latches with differential outputs. Separate Select controls
are provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and
output data is controlled by the multiplexer select controls. A logic
HIGH on LEN latches the outputs. The Master Reset (MR) overrides
all other controls to set the Q outputs LOW.
The 100 Series contains temperature compensation.
950 ps Max. D to Output
850 ps Max. LEN to Output
Split Select
Differential Outputs
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input Pulldown Resistors
ESD Protection: > 1 KV HBM, > 75 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 code V0 @ 1/8
,
Oxygen Index 28 to 34
Transistor Count = 280 devices
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Device
Package
Shipping
ORDERING INFORMATION
MC100E256FN
PLCC28
37 Units/Rail
MC100E256FNR2
PLCC28
500 Units/Reel
MARKING
DIAGRAM
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PLCC28
FN SUFFIX
CASE 776
MC100E256FN
AWLYYWW
1
28
MC100E256
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2
SEL1A
SEL1B
SEL2
VEE
LEN
MR
D1c
26
27
28
2
3
4
25 24 23
22 21 20 19
18
17
16
15
14
13
12
11
5
6
7
8
9
10
D1b D1a D2d D2c D2b D2aVCCO
Q2
Q2
VCC
Q1
Q1
VCCO
Q0
D1d D0a D0b D0c D0d VCCO Q0
1
Pinout: 28-Lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
Figure 1. Pin Assignment
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
PIN DESCRIPTION
PIN
FUNCTION
D0x D2x
ECL Data Inputs
SEL1A, SEL1B
ECL First-stage Select Inputs
SEL2
ECL Second-stage Select Input
LEN
ECL Latch Enable
MR
ECL Master Reset
Q0, Q0 Q2, Q2
ECL Data Outputs
VCC, VCCO
Positive Supply
VEE
Negative Supply
FUNCTION TABLE
Pin
State
Operation
SEL2
H
Output c/d Data
SEL1A
H
Input d Data
SEL1B
H
Input b Data
Figure 2. Logic Diagram
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
SEL1A
SEL1B
SEL2
LEN
MR
Q0
Q0
Q1
Q1
Q2
Q2
D
EN
R
D
EN
R
D
EN
R
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
MC100E256
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3
MAXIMUM RATINGS
(Note 1)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
8
V
VI
PECL Mode Input Voltage
VEE = 0 V
VI
VCC
6
V
I
C
ode
u
o age
NECL Mode Input Voltage
EE
0
VCC = 0 V
I
CC
VI
VEE
6
6
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
0 to +85
C
Tstg
Storage Temperature Range
65 to +150
C
JA
Thermal Resistance (JunctiontoAmbient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
C/W
C/W
JC
Thermal Resistance (JunctiontoCase)
std bd
28 PLCC
22 to 26
C/W
VEE
PECL Operating Range
NECL Operating Range
4.2 to 5.7
5.7 to 4.2
V
V
Tsol
Wave Solder
< 2 to 3 sec @ 248
C
265
C
1. Maximum Ratings are those values beyond which device damage may occur.
100E SERIES PECL DC CHARACTERISTICS
VCCx = 5.0 V; VEE = 0.0 V (Note 2)
0
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
69
83
69
83
79
96
mA
VOH
Output HIGH Voltage (Note 3)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 3)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage
3835
4050
4120
3835
4120
4120
3835
4120
4120
mV
VIL
Input LOW Voltage
3190
3300
3525
3190
3525
3525
3190
3525
3525
mV
IIH
Input HIGH Current
150
150
150
A
IIL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.8 V.
3. Outputs are terminated through a 50
resistor to VCC 2.0 V.
100E SERIES NECL DC CHARACTERISTICS
VCCx = 0.0 V; VEE = 5.0 V (Note 4)
0
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
69
83
69
83
79
96
mA
VOH
Output HIGH Voltage (Note 5)
1025
950
880
1025
950
880
1025
950
880
mV
VOL
Output LOW Voltage (Note 5)
1810
1705
1620
1810
1745
1620
1810
1740
1620
mV
VIH
Input HIGH Voltage
1165
950
880
1165
880
880
1165
880
880
mV
VIL
Input LOW Voltage
1810
1700
1475
1810
1475
1475
1810
1475
1475
mV
IIH
Input HIGH Current
150
150
150
A
IIL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.8 V.
5. Outputs are terminated through a 50
resistor to VCC 2.0 V.
MC100E256
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4
AC CHARACTERISTICS
VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = 5.0 V (Note 6)
0
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fMAX
Maximum Toggle Frequency
TBD
TBD
TBD
GHz
tPLH
Propagation Delay to Output
ps
tPHL
D
400
600
900
400
600
900
400
600
900
SEL1
550
775
1050
550
775
1050
550
775
1050
SEL2
450
650
900
450
650
900
450
650
900
LEN
350
500
800
350
500
800
350
500
800
MR
350
600
825
350
600
825
350
600
825
ts
Setup Time
ps
D
400
275
400
275
400
275
SEL1
600
300
600
300
600
300
SEL2
500
250
500
250
500
250
th
Hold Time
ps
D
300
275
300
275
300
275
SEL1
100
300
100
300
100
300
SEL2
200
250
200
250
200
250
tRR
Reset Recovery Time
700
600
700
600
700
600
ps
tPW
Minimum Pulse Width
ps
MR
400
400
400
tSKEW
Within-Device Skew (Note 7)
50
50
50
ps
tJITTER
CycletoCycle Jitter
TBD
TBD
TBD
ps
tr
Rise/Fall Times
ps
tf
(20 - 80%)
275
475
700
275
475
700
275
475
700
6. 100 Series: VEE can vary +0.46 V / 0.8 V.
7. Within-device skew is defined as identical transitions on similar paths through a device.
Receiver
Device
Driver
Device
Q
Q
D
D
50
50
VTT
Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 Termination of ECL Logic Devices.)
VTT = VCC 2.0 V
MC100E256
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5
Resource Reference of Application Notes
AN1404
ECLinPS Circuit Performance at NonStandard VIH Levels
AN1405
ECL Clock Distribution Techniques
AN1406
Designing with PECL (ECL at +5.0 V)
AN1503
ECLinPS I/O SPICE Modeling Kit
AN1504
Metastability and the ECLinPS Family
AN1568
Interfacing Between LVDS and ECL
AN1596
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
Using WireOR Ties in ECLinPS Designs
AN1672
The ECL Translator Guide
AND8001
Odd Number Counters Design
AND8002
Marking and Date Codes
AND8020
Termination of ECL Logic Devices
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