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Электронный компонент: MC100EL31DT

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Semiconductor Components Industries, LLC, 2000
October, 2000 Rev. 3
1
Publication Order Number:
MC10EL31/D
MC10EL31, MC100EL31
5V ECL D Flip Flop
With Set and Reset
The MC10EL/100EL31 is a D flip-flop with set and reset. The
device is functionally equivalent to the E131 device with higher
performance capabilities. With propagation delays and output
transition times significantly faster than the E131, the EL31 is ideally
suited for those applications which require the ultimate in AC
performance.
Both set and reset inputs are asynchronous, level triggered signals.
Data enters the master portion of the flip-flop when clock is LOW and
is transferred to the slave, and thus the outputs, upon a positive
transition of the clock.
The 100 Series contains temperature compensation.
475 ps Propagation Delay
2.8 GHz Toggle Frequency
ESD Protection: > 1 KV HBM, > 100 V MM
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= 4.2 V to 5.7 V
Internal Input Pulldown Resistors on D, CLK, S, and R
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL94 code V0 @ 1/8",
Oxygen Index 28 to 34
Metastability 125 ps (see Application Note AN1504)
Transistor Count = 79 devices
http://onsemi.com
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
H = MC10
K = MC100
A = Assembly Location
SO8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
TSSOP8
DT SUFFIX
CASE 948R
Device
Package
Shipping
ORDERING INFORMATION
MC10EL31D
SO8
98 Units/Rail
MC10EL31DR2
SO8
2500 Tape & Reel
MC100EL31D
SO8
98 Units/Rail
MC100EL31DR2
SO8
2500 Tape & Reel
MC10EL31DT
TSSOP8
98 Units/Rail
MC10EL31DTR2
TSSOP8 2500 Tape & Reel
MC100EL31DT
TSSOP8
98 Units/Rail
MC100EL31DTR2
TSSOP8 2500 Tape & Reel
1
8
1
8
ALYW
KEL31
1
8
ALYW
HL31
1
8
HEL31
1
8
ALYW
ALYW
KL31
1
8
MC10EL31, MC100EL31
http://onsemi.com
2
1
2
3
4
5
6
7
8
Q
V
EE
V
CC
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D
Q
CLK
R
D
S
R
S
D
L
H
X
X
X
TRUTH TABLE
S*
L
L
H
L
H
R*
L
L
L
H
H
CLK
Z
Z
X
X
X
Q
L
H
H
L
Undef
Z = LOW to HIGH Transition
S
ECL Set Input
D
ECL Data Input
R
ECL Reset Input
CLK
ECL Clock Input
Q, Q
ECL Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
PIN DESCRIPTION
PIN
FUNCTION
* Pins will default low when left open.
MAXIMUM RATINGS
(Note 1.)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
V
CC
PECL Mode Power Supply
V
EE
= 0 V
8
V
V
EE
NECL Mode Power Supply
V
CC
= 0 V
8
V
V
I
PECL Mode Input Voltage
V
EE
= 0 V
V
I
V
CC
6
V
NECL Mode Input Voltage
V
CC
= 0 V
V
I
V
EE
6
V
I
out
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
40 to +85
C
T
stg
Storage Temperature Range
65 to +150
C
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
C/W
C/W
JC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
C/W
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
C/W
C/W
JC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
5%
C/W
T
sol
Wave Solder
<2 to 3 sec @ 248
C
265
C
1. Maximum Ratings are those values beyond which device damage may occur.
MC10EL31, MC100EL31
http://onsemi.com
3
10EL SERIES PECL DC CHARACTERISTICS
V
CC
= 5.0 V; V
EE
= 0.0 V (Note 1.)
40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Power Supply Current
27
32
27
32
27
32
mA
V
OH
Output HIGH Voltage (Note 2.)
3920
4010
4110
4020
4105
4190
4090
4185
4280
mV
V
OL
Output LOW Voltage (Note 2.)
3050
3200
3350
3050
3210
3370
3050
3227
3405
mV
V
IH
Input HIGH Voltage
3770
4110
3870
4190
3940
4280
mV
V
IL
Input LOW Voltage
3050
3500
3050
3520
3050
3555
mV
I
IH
Input HIGH Current
150
150
150
A
I
IL
Input LOW Current
0.5
0.5
0.3
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.25 V / 0.5 V.
2. Outputs are terminated through a 50 ohm resistor to V
CC
2 volts.
10EL SERIES NECL DC CHARACTERISTICS
V
CC
= 0.0 V; V
EE
= 5.0 V (Note 1.)
40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Power Supply Current
27
32
27
32
27
32
mA
V
OH
Output HIGH Voltage (Note 2.)
1080
990
890
980
895
810
910
815
720
mV
V
OL
Output LOW Voltage (Note 2.)
1950
1800
1650
1950
1790
1630
1950
1773
1595
mV
V
IH
Input HIGH Voltage
1230
890
1130
810
1060
720
mV
V
IL
Input LOW Voltage
1950
1500
1950
1480
1950
1445
mV
I
IH
Input HIGH Current
150
150
150
A
I
IL
Input LOW Current
0.5
0.5
0.3
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.25 V / 0.5 V.
2. Outputs are terminated through a 50 ohm resistor to V
CC
2 volts.
100EL SERIES PECL DC CHARACTERISTICS
V
CC
= 5.0 V; V
EE
= 0.0 V (Note 1.)
40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Power Supply Current
27
32
27
32
31
37
mA
V
OH
Output HIGH Voltage (Note 2.)
3915
3995
4120
3975
4045
4120
3975
4050
4120
mV
V
OL
Output LOW Voltage (Note 2.)
3170
3305
3445
3190
3295
3380
3190
3295
3380
mV
V
IH
Input HIGH Voltage
3835
4120
3835
4120
3835
4120
mV
V
IL
Input LOW Voltage
3190
3525
3190
3525
3190
3525
mV
I
IH
Input HIGH Current
150
150
150
A
I
IL
Input LOW Current
0.5
0.5
0.5
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.8 V / 0.5 V.
2. Outputs are terminated through a 50 ohm resistor to V
CC
2 volts.
100EL SERIES NECL DC CHARACTERISTICS
V
CC
= 0.0 V; V
EE
= 5.0 V (Note 1.)
40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Power Supply Current
27
32
27
32
31
37
mA
V
OH
Output HIGH Voltage (Note 2.)
1085
1005
880
1025
955
880
1025
955
880
mV
V
OL
Output LOW Voltage (Note 2.)
1830
1695
1555
1810
1705
1620
1810
1705
1620
mV
V
IH
Input HIGH Voltage
1165
880
1165
880
1165
880
mV
V
IL
Input LOW Voltage
1810
1475
1810
1475
1810
1475
mV
I
IH
Input HIGH Current
150
150
150
A
I
IL
Input LOW Current
0.5
0.5
0.5
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.8 V / 0.5 V.
2. Outputs are terminated through a 50 ohm resistor to V
CC
2 volts.
MC10EL31, MC100EL31
http://onsemi.com
4
AC CHARACTERISTICS
V
CC
= 5.0 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
= 5.0 V (Note 1.)
40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Toggle Frequency
2.0
2.5
2.2
2.8
2.2
2.8
GHz
t
PLH
t
PHL
Propagation Delay
to Output
CLK
S, R
315
295
465
455
630
630
375
355
475
465
590
590
430
400
530
510
645
645
ps
t
S
t
H
Setup Time
Hold Time
150
250
0
100
150
250
0
100
150
250
0
100
ps
t
RR
Set/Reset Recovery
400
200
400
200
400
200
ps
t
PW
Minimum Pulse Width
CLK, Set, Reset
400
400
400
ps
tJITTER
CycletoCycle Jitter
TBD
TBD
TBD
ps
t
r
t
f
Output Rise/Fall Times Q
(20% 80%)
100
225
350
100
225
350
100
225
350
ps
1. 10 Series: V
EE
can vary +0.25 V / 0.5 V.
100 Series: V
EE
can vary +0.8 V / 0.5 V.
V TT = V CC 2.0 V
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 Termination of ECL Logic Devices.)
W
Driver
Device
Receiver
Device
Q
Qb
D
Db
50
W
50
V TT
MC10EL31, MC100EL31
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5
Resource Reference of Application Notes
AN1404
ECLinPS Circuit Performance at NonStandard V
IH
Levels
AN1405
ECL Clock Distribution Techniques
AN1406
Designing with PECL (ECL at +5.0 V)
AN1503
ECLinPS I/O SPICE Modeling Kit
AN1504
Metastability and the ECLinPS Family
AN1560
Low Voltage ECLinPS SPICE Modeling Kit
AN1568
Interfacing Between LVDS and ECL
AN1596
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
Using WireOR Ties in ECLinPS Designs
AN1672
The ECL Translator Guide
AND8001
Odd Number Counters Design
AND8002
Marking and Date Codes
AND8020
Termination of ECL Logic Devices