Semiconductor Components Industries, LLC,2004
October, 2004 - Rev. 10
1
Publication Order Number:
MC100EP196/D
MC100EP196
3.3V ECL Programmable
Delay Chip with FTUNE
The MC100EP196 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tuneability in
delay using the FTUNE pin. The FTUNE input takes an analog voltage
from V
CC
to V
EE
to fine tune the output delay from 0 to 60 ps.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay increment
of the EP196 has a digitally selectable resolution of about 10 ps and a net
range of up to 10.2 ns. The required delay is selected by the 10 data select
inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on
LEN allows a transparent LOAD mode of real time delay values by
D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD
current values present against any subsequent changes in D[10:0]. The
approximate delay values for varying tap numbers correlating to D0 (LSB)
through D9 (MSB) are shown in Table 5.
Because the EP196 is designed using a chain of multiplexers, it has a
fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all "1" states on D[0:9] with SETMAX LOW
to all "0" states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to "D0", the minimum increment.
Select input pins, D[10:0], may be threshold controlled by
combinations of interconnects between V
EF
(pin 7) and V
CF
(pin 8)
for LVCMOS, ECL, or LVTTL level signals. LVTTL and LVCMOS
operation is available in PECL mode only. For LVCMOS input levels,
leave V
CF
and V
EF
open. For ECL operation, short V
CF
and V
EF
(pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to V
CF
and leave open V
EF
pin. The 1.5 V reference voltage
to V
CF
pin can be accomplished by placing a 2.2 k
W resistor between
V
CF
and V
EE
for 3.3 V power supply.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
Maximum Frequency > 1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.4 ns to 12.4 ns
10 ps Increments
PECL Mode Operating Range:
V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= -3.0 V to -3.6 V
Open Input Default State
Safety Clamp on Inputs
A Logic High on the EN Pin Will Force Q to Logic
Low
D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
Inputs
V
BB
Output Reference Voltage
32
1
MC100
AWLYYWW
EP196
LQFP-32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
ORDERING INFORMATION
MC100EP196
http://onsemi.com
3
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
23, 25, 26, 27,
29, 30, 31, 32,
1, 2
D[0:9]
LVCMOS, LVTTL,
ECL Input
LOW
Single-ended Parallel Data Inputs [0:9]. Internal 75 k
W
to V
EE
.
(Note 1)
3
D[10]
LVCMOS, LVTTL,
ECL Input
LOW
Single-ended CASCADE/CASCADE Control Input. Internal 75 k
W
to V
EE
. (Note 1)
4
IN
ECL Input
LOW
Noninverted Differential Input. Internal 75 k
W
to V
EE
.
5
IN
ECL Input
HIGH
Inverted Differential Input. Internal 75 k
W
to V
EE
and 36.5 k
W
to
V
CC
.
6
V
BB
-
-
ECL Reference Voltage Output
7
V
EF
-
-
Reference Voltage for ECL Mode Connection
8
V
CF
-
-
LVCMOS, ECL, OR LVTTL Input Mode Select
9, 28
V
EE
-
-
Negative Supply Voltage. All V
EE
Pins must be Externally Con-
nected to Power Supply to Guarantee Proper Operation. (Note 2)
13, 18, 19, 22
V
CC
-
-
Positive Supply Voltage. All V
CC
Pins must be externally Con-
nected to Power Supply to Guarantee Proper Operation. (Note 2)
10
LEN
ECL Input
LOW
Single-ended D pins LOAD / HOLD input. Internal 75 k
W
to V
EE
.
11
SETMIN
ECL Input
LOW
Single-ended Minimum Delay Set Logic Input. Internal 75 k
W
to
V
EE
. (Note 1)
12
SETMAX
ECL Input
LOW
Single-ended Maximum Delay Set Logic Input. Internal 75 k
W
to
V
EE
. (Note 1)
14
CASCADE
ECL Output
-
Inverted Differential Cascade Output for D[10] Input. Typically Ter-
minated with 50
W
to V
TT
= V
CC
- 2 V.
15
CASCADE
ECL Output
-
Noninverted Differential Cascade Output for D[10] Input. Typically
Terminated with 50
W
to V
TT
= V
CC
- 2 V.
16
EN
ECL Input
LOW
Single-ended Output Enable Pin. Internal 75 k
W
to V
EE
.
17
FTUNE
Analog Input
-
Fine Tuning Input.
21
Q
ECL Output
-
Noninverted Differential Output. Typically Terminated with 50
W
to
V
TT
= V
CC
- 2 V.
20
Q
ECL Output
-
Inverted Differential Output. Typically Terminated with 50
W
to
V
TT
= V
CC
- 2 V.
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation.
MC100EP196
http://onsemi.com
4
Table 2. CONTROL PIN
Pin
State
Function
EN
LOW (Note 3)
Input Signal is Propagated to the Output
HIGH
Output Holds Logic Low State
LEN
LOW (Note 3)
Transparent or LOAD mode for real time delay values present on D[0:10].
HIGH
LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]
are not recognized and do not affect delay.
SETMIN
LOW (Note 3)
Output Delay set by D[0:10]
HIGH
Set Minimum Output Delay
SETMAX
LOW (Note 3)
Output Delay set by D[0:10]
HIGH
Set Maximum Output Delay
D10
LOW
CASCADE Output LOW, CASCADE Output HIGH
HIGH
CASCADE Output LOW, CASCADE Output High
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE
Pin
State
Function
V
CF
V
EF
Pin (Note 4)
ECL Mode
V
CF
No Connect
LVCMOS Mode
V
CF
1.5 V
$
100 mV
LVTTL Mode (Note 5)
4. Short V
CF
(pin 8) and V
EF
(pin 7).
5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, R
CF
(suggested resistor value
is 2.2 k
W
$
5%), between V
CF
and V
EE
pins.
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
CONTROL DATA SELECT INPUTS PINS (D [0:10])
POWER SUPPLY
LVCMOS
LVTTL
LVPECL
LVNECL
PECL Mode Operating Range
YES
YES
YES
N/A
NECL Mode Operating Range
N/A
N/A
N/A
YES
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