Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 4
1
Publication Order Number:
MC10H644/D
MC10H644, MC100H644
68030/040 PECL to TTL
Clock Driver
The MC10H/100H644 generates the necessary clocks for the
68030, 68040 and similar microprocessors. The device is functionally
equivalent to the H640, but with fewer outputs in a smaller outline
20lead PLCC package. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of
parttopart skew, withinpart skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced
to +5.0V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H644 also uses differential ECL internally to achieve its
superior skew characteristic.
The H644 includes dividebytwo and dividebyfour stages, both
to achieve the necessary duty cycle and skew to generate MPU clocks
as required. A typical 50MHz processor application would use an
input clock running at 100MHz, thus obtaining output clocks at
50MHz and 25MHz (see Logic Symbol).
The 10H version is compatible with MECL 10H
TM
ECL logic levels,
while the 100H version is compatible with 100K levels (referenced
to +5.0V).
Generates Clocks for 68030/040
Meets 68030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and ECL Power/Ground Pins
Within Device Skew on Similar Paths is 0.5 ns
Asynchronous Reset
Single +5.0V Supply
Function
Reset (R): LOW on RESET forces all Q outputs LOW and all Q
outputs HIGH.
Synchronized Outputs: The device is designed to have the POS
edges of the
2 and
4 outputs synchronized.
Select (SEL): LOW selects the PECL input source (DE/DE). HIGH
selects the TTL input source (DT).
The H644 also contains circuitry to force a stable state of the PECL
input differential pair, should both sides be left open. In this case, the
DE side of the input is pulled LOW, and DE goes HIGH.
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Device
Package
Shipping
ORDERING INFORMATION
MC10H644FN
PLCC20
37 Units/Rail
MARKING
DIAGRAM
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PLCC20
FN SUFFIX
CASE 775
10H644
AWLYYWW
1
MC100H644FN
PLCC20
37 Units/Rail
MC10H644, MC100H644
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2
GT
Q3
GT
Q2
GT
Q4
VT
Q5
GT
R
VE
DE
VBB
DE
GE
Q1
VT
Q0
SEL
DT
19
18
13
17
16
15
14
12
11
10
9
4
5
6
7
8
20
1
2
3
Pinout: 20Lead PLCC (Top View)
4
VBB
TTL OUTPUTS
Q5
Q4
Q3
Q2
Q1
Q0
2
2:1 MUX
DE
(ECL)
DE
(ECL)
DT
(TTL)
SEL
(TTL)
R
(TTL)
LOGIC DIAGRAM
PIN NAMES
PIN
FUNCTION
GT
VT
VE
GE
DE, DE
VBB
DT
Qn, Qn
SEL
R
TTL Ground (0V)
TTL VCC (+5.0V)
ECL VCC (+5.0V)
ECL Ground (0V)
ECL Signal Input (positive ECL)
VBB Reference Output
TTL Signal Input
Signal Outputs (TTL)
Input Select (TTL)
Reset (TTL)
MC10H644, MC100H644
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3
AC CHARACTERISTICS (VT = VE = 5.0 V
5%)
0
C
25
C
85
C
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Unit
Condition
tPLH
Propagation Delay ECL
D to Output
All Outputs
5.8
6.8
5.7
6.7
6.1
7.1
ns
CL = 50pF
tPLH
Propagation Delay TTL
D to Output
5.7
6.7
5.7
6.7
6.0
7.0
ns
CL = 50pF
tskwd*
WithinDevice Skew
Q0, 1, 4, 5
0.5
0.5
0.5
ns
CL = 50pF
tskwd*
WithinDevice Skew
Q2, Q3
0.5
0.5
0.5
ns
CL = 50pF
tskwd*
WithinDevice Skew
All Outputs
1.5
1.5
1.5
ns
CL = 50pF
tskpp*
ParttoPart Skew
Q0, 1, 4, 5
1.0
1.0
1.0
ns
CL = 50pF
tPD
Propagation Delay
R to Output
All Outputs
4.3
7.3
4.3
7.3
4.5
7.5
ns
CL = 50pF
tR
tF
Output Rise/Fall Time
0.8V 2.0V
All Outputs
1.6
1.6
1.6
ns
CL = 50pF
fmax
Maximum Input Frequency
135
135
135
MHz
CL = 50pF
TW
Minimum Pulse Width Reset
1.5
1.5
1.5
ns
trr
Reset Recovery Time
1.25
1.25
1.25
ns
TPW
Pulse Width Out High or
Low @ fin = 100 MHz
and CL = 50 pf
Q0, 1
9.5
10.5
9.5
10.5
9.5
10.5
ns
CL = 50pf
Relative 1.5V
TS
Setup Time
SEL to DE, DT
2.0
2.0
2.0
ns
TH
Hold Time
SEL to DE, DT
2.0
2.0
2.0
ns
* Skews are specified for Identical Edges
MC10H644, MC100H644
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4
DC CHARACTERISTICS (VT = VE = 5.0 V
5%)
0
C
25
C
85
C
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Unit
Condition
IEE
Power Supply Current
ECL
65
65
65
mA
VE Pin
ICC
TTL
85
85
85
mA
Total all VT pins
TTL DC CHARACTERISTICS (VT = VE = 5.0 V
5%)
0
C
25
C
85
C
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Unit
Condition
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
2.0
0.8
2.0
0.8
2.0
0.8
V
IIH
Input HIGH Current
20
100
20
100
20
100
A
VIN = 2.7 V
VIN = 7.0 V
IIL
Input LOW Current
0.6
0.6
0.6
mA
VIN = 0.5 V
VOH
Output HIGH Voltage
2.5
2.0
2.5
2.0
2.5
2.0
V
IOH = 3.0 mA
IOH = 24 mA
VOL
Output LOW Voltage
0.5
0.5
0.5
V
IOL = 24 mA
VIK
Input Clamp Voltage
1.2
1.2
1.2
V
IIN = 18 mA
IOS
Output Short Circuit Current
100
225
100
225
100
225
mA
VOUT = 0 V
10H PECL DC CHARACTERISTICS (VT = VE = 5.0 V
5%)
0
C
25
C
85
C
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Unit
Condition
IINH
IINL
Input HIGH Current
Input LOW Current
0.5
225
0.5
175
0.5
175
A
VIH*
VIL*
Input HIGH Voltage
Input LOW Voltage
3.83
3.05
4.16
3.52
3.87
3.05
4.19
3.52
3.94
3.05
4.28
3.55
V
VE = 5.0 V
VBB*
Output Reference Voltage
3.62
3.73
3.65
3.75
3.69
3.81
V
VE = 5.0 V
100H PECL DC CHARACTERISTICS (VT = VE = 5.0 V
5%)
0
C
25
C
85
C
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Unit
Condition
IINH
IINL
Input HIGH Current
Input LOW Current
0.5
225
0.5
175
0.5
175
A
VIH*
VIL*
Input HIGH Voltage
Input LOW Voltage
3.835
3.19
4.12
3.525
3.835
3.19
4.12
3.525
3.835
3.19
4.12
3.525
V
VE = 5.0 V
VBB*
Output Reference Voltage
3.62
3.74
3.62
3.74
3.62
3.74
V
VE = 5.0 V
* NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0 V.
Only corresponds to ECL Clock Inputs.
MC10H644, MC100H644
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5
PACKAGE DIMENSIONS
PLCC20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 77502
ISSUE C
NOTES:
1. DATUMS L, M, AND N DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM T, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
M
N
L
Y BRK
W
V
D
D
S
LM
M
0.007 (0.180)
N
S
T
S
LM
M
0.007 (0.180)
N
S
T
S
LM
S
0.010 (0.250)
N
S
T
X
G1
B
U
Z
VIEW DD
20
1
S
LM
M
0.007 (0.180)
N
S
T
S
LM
M
0.007 (0.180)
N
S
T
S
LM
S
0.010 (0.250)
N
S
T
C
G
VIEW S
E
J
R
Z
A
0.004 (0.100)
T
SEATING
PLANE
S
LM
M
0.007 (0.180)
N
S
T
S
LM
M
0.007 (0.180)
N
S
T
H
VIEW S
K
K1
F
G1
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.385
0.395
9.78
10.03
B
0.385
0.395
9.78
10.03
C
0.165
0.180
4.20
4.57
E
0.090
0.110
2.29
2.79
F
0.013
0.019
0.33
0.48
G
0.050 BSC
1.27 BSC
H
0.026
0.032
0.66
0.81
J
0.020
0.51
K
0.025
0.64
R
0.350
0.356
8.89
9.04
U
0.350
0.356
8.89
9.04
V
0.042
0.048
1.07
1.21
W
0.042
0.048
1.07
1.21
X
0.042
0.056
1.07
1.42
Y
0.020
0.50
Z
2
10
2
10
G1
0.310
0.330
7.88
8.38
K1
0.040
1.02
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