Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 3
1
Publication Order Number:
MC14013B/D
MC14013B
Dual Type D Flip-Flop
The MC14013B dual type D flipflop is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. Each flipflop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
elements or as type T flipflops for counter and toggle applications.
Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic EdgeClocked FlipFlop Design
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positivegoing
edge of the clock pulse
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
PinforPin Replacement for CD4013B
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Ambient Temperature Range
55 to +125
C
T
stg
Storage Temperature Range
65 to +150
C
T
L
Lead Temperature
(8Second Soldering)
260
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
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A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14013BCP
PDIP14
2000/Box
MC14013BD
SOIC14
55/Rail
MC14013BDR2
SOIC14
2500/Tape & Reel
MC14013BDT
TSSOP14
MC14013BF
SOEIAJ14
96/Rail
See Note 1.
MARKING
DIAGRAMS
1
14
PDIP14
P SUFFIX
CASE 646
MC14013BCP
AWLYYWW
SOIC14
D SUFFIX
CASE 751A
TSSOP14
DT SUFFIX
CASE 948G
1
14
14013B
AWLYWW
14
013B
ALYW
1
14
SOEIAJ14
F SUFFIX
CASE 965
1
14
MC14013B
AWLYWW
MC14013BFEL
SOEIAJ14
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MC14013BDTR2
TSSOP14 2500/Tape & Reel
MC14013B
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3
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
55
_
C
25
_
C
125
_
C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
Output Voltage
"0" Level
V
in
= V
DD
or 0
V
OL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
V
in
= 0 or V
DD
"1" Level
V
OH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
--
--
--
1.5
3.0
4.0
--
--
--
2.25
4.50
6.75
1.5
3.0
4.0
--
--
--
1.5
3.0
4.0
Vdc
(V
O
= 0.5 or 4.5 Vdc)
"1" Level
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
--
--
--
3.5
7.0
11
2.75
5.50
8.25
--
--
--
3.5
7.0
11
--
--
--
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc)
Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
--
--
--
--
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
--
--
--
--
1.7
0.36
0.9
2.4
--
--
--
--
mAdc
(V
OL
= 0.4 Vdc)
Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
--
--
--
0.51
1.3
3.4
0.88
2.25
8.8
--
--
--
0.36
0.9
2.4
--
--
--
mAdc
Input Current
I
in
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
(V
in
= 0)
C
in
--
--
--
--
5.0
7.5
--
--
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
--
--
--
1.0
2.0
4.0
--
--
--
0.002
0.004
0.006
1.0
2.0
4.0
--
--
--
30
60
120
Adc
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
I
T
= (0.75
A/kHz) f + I
DD
I
T
= (1.5
A/kHz) f + I
DD
I
T
= (2.3
A/kHz) f + I
DD
Adc
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
50) Vfk
where: I
T
is in
A (per package), C
L
in pF, V = (V
DD
V
SS
) in volts, f in kHz is input frequency, and k = 0.002.
MC14013B
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4
SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Symbol
V
DD
Min
Typ
(8.)
Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
--
--
--
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 90 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 42 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 25 ns
t
PLH
t
PHL
5.0
10
15
--
--
--
175
75
50
350
150
100
ns
Set to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 90 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 42 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 25 ns
5.0
10
15
--
--
--
175
75
50
350
150
100
Reset to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 265 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 67 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 50 ns
5.0
10
15
--
--
--
225
100
75
450
200
150
Setup Times
(9.)
t
su
5.0
10
15
40
20
15
20
10
7.5
--
--
--
ns
Hold Times
(9.)
t
h
5.0
10
15
40
20
15
20
10
7.5
--
--
--
ns
Clock Pulse Width
t
WL
, t
WH
5.0
10
15
250
100
70
125
50
35
--
--
--
ns
Clock Pulse Frequency
f
cl
5.0
10
15
--
--
--
4.0
10
14
2.0
5.0
7.0
MHz
Clock Pulse Rise and Fall Time
t
TLH
t
THL
5.0
10
15
--
--
--
--
--
--
15
5.0
4.0
s
Set and Reset Pulse Width
t
WL
, t
WH
5.0
10
15
250
100
70
125
50
35
--
--
--
ns
Removal Times
Set
t
rem
5
10
15
80
45
35
0
5
5
--
--
--
ns
Reset
5
10
15
50
30
25
35
10
5
--
--
--
7. The formulas given are for the typical characteristics only at 25
_
C.
8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
9. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.
LOGIC DIAGRAM (1/2 of Device Shown)
R
C
D
S
C
C
C
C
C
C
C
C
C
C
Q
Q
MC14013B
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5
Figure 1. Dynamic Signal Waveforms
(Data, Clock, and Output)
Figure 2. Dynamic Signal Waveforms
(Set, Reset, Clock, and Output)
20 ns
20 ns
D
C
Q
90%
50%
10%
t
su
(H)
t
su (L)
t
h
t
WH
t
WL
90%
50%
10%
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
t
TLH
t
THL
t
PHL
t
PLH
90%
50%
10%
Inputs R and S low.
1
f
cl
20 ns
20 ns
SET OR
RESET
CLOCK
Q OR Q
90%
50%
10%
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
20 ns
20 ns
t
rem
90%
50%
10%
50%
t
PLH
t
PHL
t
w
20 ns
t
w
TYPICAL APPLICATIONS
nSTAGE SHIFT REGISTER
BINARY RIPPLE UPCOUNTER (Divideby2
n
)
MODIFIED RING COUNTER (Divideby(n+1))
D
CLOCK
n
th
2
1
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK
n
th
2
1
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
Q
T FLIPFLOP
n
th
2
1
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK
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