Semiconductor Components Industries, LLC, 2005
February, 2005 - Rev. 5
1
Publication Order Number:
MC14014B/D
MC14014B, MC14021B
8-Bit Static Shift Register
The MC14014B and MC14021B 8-bit static shift registers are
constructed with MOS P-channel and N-channel enhancement mode
devices in a single monolithic structure. These shift registers find primary
use in parallel-to-serial data conversion, synchronous and asynchronous
parallel input, serial output data queueing; and other general purpose
register applications requiring low power and/or high noise immunity.
Features
Synchronous Parallel Input/Serial Output (MC14014B)
Asynchronous Parallel Input/Serial Output (MC14021B)
Synchronous Serial Input/Serial Output
Full Static Operation
"Q" Outputs from Sixth, Seventh, and Eighth Stages
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low-power TTL Loads or One Low-power
Schottky TTL Load Over the Rated Temperature Range
MC14014B Pin-for-Pin Replacement for CD4014B
MC14021B Pin-for-Pin Replacement for CD4021B
Pb-Free Packages are Available*
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
- 0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
- 0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
10
mA
P
D
Power Dissipation, per Package
(Note 1)
500
mW
T
A
Ambient Temperature Range
- 55 to +125
C
T
stg
Storage Temperature Range
- 65 to +150
C
T
L
Lead Temperature
(8-Second Soldering)
260
C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
PDIP-16
P SUFFIX
CASE 648
MC140xxBCP
AWLYYWW
SOIC-16
D SUFFIX
CASE 751B
140xxB
AWLYWW
xx
= Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
SOEIAJ-16
F SUFFIX
CASE 966
MC140xxB
AWLYWW
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
16
1
1
16
1
16
MC14014B, MC14021B
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
- 55
_
C
25
_
C
125
_
C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
Output Voltage
"0" Level
V
in
= V
DD
or 0
V
OL
5.0
10
15
-
-
-
0.05
0.05
0.05
-
-
-
0
0
0
0.05
0.05
0.05
-
-
-
0.05
0.05
0.05
Vdc
V
in
= 0 or V
DD
"1" Level
V
OH
5.0
10
15
4.95
9.95
14.95
-
-
-
4.95
9.95
14.95
5.0
10
15
-
-
-
4.95
9.95
14.95
-
-
-
Vdc
Input Voltage
"0" Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
-
-
-
1.5
3.0
4.0
-
-
-
2.25
4.50
6.75
1.5
3.0
4.0
-
-
-
1.5
3.0
4.0
Vdc
(V
O
= 0.5 or 4.5 Vdc)
"1" Level
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
-
-
-
3.5
7.0
11
2.75
5.50
8.25
-
-
-
3.5
7.0
11
-
-
-
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc)
Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
-
-
-
-
2.4
0.51
- 1.3
- 3.4
4.2
0.88
2.25
- 8.8
-
-
-
-
1.7
- 0.36
0.9
- 2.4
-
-
-
-
mAdc
(V
OL
= 0.4 Vdc)
Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
-
-
-
0.51
1.3
3.4
0.88
2.25
8.8
-
-
-
0.36
0.9
2.4
-
-
-
mAdc
Input Current
I
in
15
-
0.1
-
0.00001
0.1
-
1.0
m
Adc
Input Capacitance
(V
in
= 0)
C
in
-
-
-
-
5.0
7.5
-
-
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
-
-
-
5.0
10
15
-
-
-
0.005
0.010
0.015
5.0
10
15
-
-
-
150
300
600
m
Adc
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
I
T
= (0.75
m
A/kHz) f + I
DD
I
T
= (1.50
m
A/kHz) f + I
DD
I
T
= (2.25
m
A/kHz) f + I
DD
m
Adc
2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
3. The formulas given are for the typical characteristics only at 25
_
C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
- 50) Vfk
where: I
T
is in
m
A (per package), C
L
in pF, V = (V
DD
- V
SS
) in volts, f in kHz is input frequency, and k = 0.0015.
MC14014B, MC14021B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Symbol
V
DD
Vdc
Min
Typ
(Note 6)
Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
-
-
-
100
50
40
200
100
80
ns
Propagation Delay Time (Clock to Q, P/S to Q)
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 315 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 137 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 90 ns
t
PLH
,
t
PHL
5.0
10
15
-
-
-
400
170
115
800
340
230
ns
Clock Pulse Width
t
WH
5.0
10
15
400
175
135
150
75
40
-
-
-
ns
Clock Frequency
f
cl
5.0
10
15
-
-
-
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Parallel/Serial Control Pulse Width
t
WH
5.0
10
15
400
175
135
150
75
40
-
-
-
ns
Setup Time
P/S to Clock
t
su
5.0
10
15
200
100
80
100
50
40
-
-
-
ns
Hold Time
Clock to P/S
t
h
5.0
10
15
20
20
25
2.5
10
0
-
-
-
ns
Setup Time
Data (Parallel or Serial) to
Clock or P/S
t
su
5.0
10
15
350
80
60
150
50
30
-
-
-
ns
Hold Time
Clock to D
s
t
h
5.0
10
15
45
35
35
0
0
5
-
-
-
ns
Hold Time
Clock to P
n
t
h
5.0
10
15
50
45
45
25
20
20
-
-
-
ns
Input Clock Rise Time
t
r(cl)
5.0
10
15
-
-
-
-
-
-
15
5
4
m
s
5. The formulas given are for the typical characteristics only at 25
_
C.
6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
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