Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 3
1
Publication Order Number:
MC14015B/D
MC14015B
Dual 4-Bit Static
Shift Register
The MC14015B dual 4bit static shift register is constructed with
MOS Pchannel and Nchannel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4state serialinput/paralleloutput registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D masterslave flipflops. Data is shifted
from one stage to the next during the positivegoing clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serialtoparallel conversion where low power
dissipation and/or noise immunity is desired.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic EdgeClocked FlipFlop Design --
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going
edge of the clock pulse.
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range.
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Ambient Temperature Range
55 to +125
C
T
stg
Storage Temperature Range
65 to +150
C
T
L
Lead Temperature
(8Second Soldering)
260
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
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A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14015BCP
PDIP16
2000/Box
MC14015BD
SOIC16
48/Rail
MC14015BDR2
SOIC16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP16
P SUFFIX
CASE 648
MC14015BCP
AWLYYWW
SOIC16
D SUFFIX
CASE 751B
1
16
14015B
AWLYWW
SOEIAJ16
F SUFFIX
CASE 966
1
16
MC14015B
AWLYWW
TSSOP16
DT SUFFIX
CASE 948F
14
015B
ALYW
1
16
MC14015BDT
TSSOP16 2000/Tape & Reel
MC14015BF
SOEIAJ16
See Note 1.
MC14015BFEL
SOEIAJ16
See Note 1.
MC14015B
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3
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
55
_
C
25
_
C
125
_
C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
Output Voltage
"0" Level
V
in
= V
DD
or 0
V
OL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
V
in
= 0 or V
DD
"1" Level
V
OH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(V
O
= 4.5 or .05 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
--
--
--
1.5
3.0
4.0
--
--
--
2.25
4.50
6.75
1.5
3.0
4.0
--
--
--
1.5
3.0
4.0
Vdc
(V
O
= 0.5 or 4.5 Vdc)
"1" Level
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
--
--
--
3.5
7.0
11
2.75
5.50
8.25
--
--
--
3.5
7.0
11
--
--
--
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc)
Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
--
--
--
--
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
--
--
--
--
1.7
0.36
0.9
2.4
--
--
--
--
mAdc
(V
OL
= 0.4 Vdc)
Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
--
--
--
0.51
1.3
3.4
0.88
2.25
8.8
--
--
--
0.36
0.9
2.4
--
--
--
mAdc
Input Current
I
in
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
(V
in
= 0)
C
in
--
--
--
--
5.0
7.5
--
--
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
--
--
--
5.0
10
20
--
--
--
0.005
0.010
0.015
5.0
10
20
--
--
--
150
300
600
Adc
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
I
T
= (1.2
A/kHz)f + I
DD
I
T
= (2.4
A/kHz)f + I
DD
I
T
= (3.6
A/kHz)f + I
DD
Adc
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
50) Vfk
where: I
T
is in
A (per package), C
L
in pF, V = (V
DD
V
SS
) in volts, f in kHz is input frequency, and k = 0.002.
MC14015B
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4
SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Symbol
V
DD
Min
Typ
(8.)
Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
--
--
--
100
50
40
200
100
80
ns
Propagation Delay Time
Clock, Data to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 225 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 92 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 65 ns
Reset to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 375 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 147 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 95 ns
t
PLH
,
t
PHL
5.0
10
15
5.0
10
15
--
--
--
--
--
--
310
125
90
460
180
120
750
250
170
750
250
170
ns
Clock Pulse Width
t
WH
5.0
10
15
400
175
135
185
85
55
--
--
--
ns
Clock Pulse Frequency
f
cl
5.0
10
15
--
--
--
2.0
6.0
7.5
1.5
3.0
3.75
MHz
Clock Pulse Rise and Fall Times
t
TLH
, t
THL
5.0
10
15
--
--
--
--
--
--
15
5
4
s
Reset Pulse Width
t
WH
5.0
10
15
400
160
120
200
80
60
--
--
--
ns
Setup Time
t
su
5.0
10
15
350
100
75
100
50
40
--
--
--
ns
7. The formulas given are for typical characteristics only at 25
_
C.
8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
Figure 1. Power Dissipation Test Circuit and Waveform
PULSE
GENERATOR
2
CLOCK
DATA
50%
1
f
PULSE
GENERATOR
1
500
F
V
DD
I
D
0.01
F
CERAMIC
C
L
Q0
Q1
Q2
Q3
D
C
R
V
SS
C
L
C
L
C
L
V
DD
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