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Электронный компонент: MC14016BCP

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Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 3
1
Publication Order Number:
MC14016B/D
MC14016B
Quad Analog Switch/
Quad Multiplexer
The MC14016B quad bilateral switch is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. Each MC14016B consists of four independent
switches capable of controlling either digital or analog signals. The
quad bilateral switch is used in signal gating, chopper, modulator,
demodulator and CMOS logic implementation.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linearized Transfer Characteristics
Low Noise -- 12 nV/
Cycle, f
1.0 kHz typical
PinforPin Replacements for CD4016B, CD4066B (Note improved
transfer characteristic design causes more parasitic coupling
capacitance than CD4016)
For Lower R
ON
, Use The HC4016 HighSpeed CMOS Device or
The MC14066B
This Device Has Inputs and Outputs Which Do Not Have ESD
Protection. Antistatic Precautions Must Be Taken.
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5
V
I
in
Input Current (DC or Transient)
per Control Pin
10
mA
I
SW
Switch Through Current
25
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Ambient Temperature Range
55 to +125
C
T
stg
Storage Temperature Range
65 to +150
C
T
L
Lead Temperature
(8Second Soldering)
260
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14016BCP
PDIP14
2000/Box
MC14016BD
SOIC14
55/Rail
MC14016BDR2
SOIC14
2500/Tape & Reel
MC14016BF
SOEIAJ14
See Note 1.
MARKING
DIAGRAMS
1
14
PDIP14
P SUFFIX
CASE 646
MC14016BCP
AWLYYWW
SOIC14
D SUFFIX
CASE 751A
1
14
14016B
AWLYWW
SOEIAJ14
F SUFFIX
CASE 965
1
14
MC14016B
AWLYWW
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MC14016BFEL
SOEIAJ14
See Note 1.
MC14016B
http://onsemi.com
2
BLOCK DIAGRAM
CONTROL 1
IN 1
CONTROL 2
IN 2
CONTROL 3
IN 3
CONTROL 4
IN 4
OUT 1
OUT 2
OUT 3
OUT 4
13
1
5
4
6
8
12
11
2
3
9
10
V
DD
= PIN 14
V
SS
= PIN 7
Control
Switch
0 = V
SS
Off
1 = V
DD
On
PIN ASSIGNMENT
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUT 4
IN 4
CONTROL 4
CONTROL 1
V
DD
IN 3
OUT 3
IN 2
OUT 2
OUT 1
IN 1
V
SS
CONTROL 3
CONTROL 2
LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
CONTROL
OUT
IN
LOGIC DIAGRAM RESTRICTIONS
V
SS
V
in
V
DD
V
SS
V
out
V
DD
MC14016B
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3
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
55
_
C
25
_
C
125
_
C
Characteristic
Figure
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
Input Voltage
Control Input
1
V
IL
5.0
10
15
--
--
--
--
--
--
--
--
--
1.5
1.5
1.5
0.9
0.9
0.9
--
--
--
--
--
--
Vdc
V
IH
5.0
10
15
--
--
--
--
--
--
3.0
8.0
13
2.0
6.0
11
--
--
--
--
--
--
--
--
--
Vdc
Input Current Control
--
I
in
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
Control
Switch Input
Switch Output
Feed Through
--
C
in
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
5.0
5.0
5.0
0.2
--
--
--
--
--
--
--
--
--
--
--
--
pF
Quiescent Current
(Per Package)
(5.)
2,3
I
DD
5.0
10
15
--
--
--
0.25
0.5
1.0
--
--
--
0.0005
0.0010
0.0015
0.25
0.5
1.0
--
--
--
7.5
15
30
Adc
"ON" Resistance
(V
C
= V
DD
, R
L
= 10 k
)
(V
in
= + 5.0 Vdc)
(V
in
= 5.0 Vdc) V
SS
= 5.0 Vdc
(V
in
=
0.25 Vdc)
4,5,6
R
ON
5.0
--
--
--
600
600
600
--
--
--
--
--
300
300
280
660
660
660
--
--
--
--
--
840
840
840
Ohms
(V
in
= + 7.5 Vdc)
(V
in
= 7.5 Vdc) V
SS
= 7.5 Vdc
(V
in
=
0.25 Vdc)
7.5
--
--
--
360
360
360
--
--
--
240
240
180
400
400
400
--
--
--
520
520
520
(V
in
= + 10 Vdc)
(V
in
= + 0.25 Vdc) V
SS
= 0 Vdc
(V
in
= + 5.6 Vdc)
10
--
--
--
600
600
600
--
--
--
260
310
310
660
660
660
--
--
--
840
840
840
(V
in
= + 15 Vdc)
(V
in
= + 0.25 Vdc) V
SS
= 0 Vdc
(V
in
= + 9.3 Vdc)
15
--
--
--
360
360
360
--
--
--
260
260
300
400
400
400
--
--
--
520
520
520
"ON" Resistance
Between any 2 circuits in a common
package
(V
C
= V
DD
)
(V
in
=
5.0 Vdc, V
SS
= 5.0 Vdc)
(V
in
=
7.5 Vdc, V
SS
= 7.5 Vdc)
--
R
ON
5.0
7.5
--
--
--
--
--
--
15
10
--
--
--
--
--
--
Ohms
Input/Output Leakage Current
(V
C
= V
SS
)
(V
in
= + 7.5, V
out
= 7.5 Vdc)
(V
in
= 7.5, V
out
= + 7.5 Vdc)
--
--
7.5
7.5
--
--
0.1
0.1
--
--
0.0015
0.0015
0.1
0.1
--
--
1.0
1.0
Adc
NOTE: All unused inputs must be returned to V
DD
or V
SS
as appropriate for the circuit application.
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5. For voltage drops across the switch (
V
switch
) > 600 mV ( > 300 mV at high temperature), excessive V
DD
current may be drawn; i.e., the
current out of the switch may contain both V
DD
and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.
MC14016B
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4
ELECTRICAL CHARACTERISTICS
(6.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Figure
Symbol
V
DD
Vdc
Min
Typ
(7.)
Max
Unit
Propagation Delay Time (V
SS
= 0 Vdc)
V
in
to V
out
(V
C
= V
DD
, R
L
= 10 k
)
7
t
PLH
,
t
PHL
5.0
10
15
--
--
--
15
7.0
6.0
45
15
12
ns
Control to Output
(V
in
v
10 Vdc, R
L
= 10 k
)
8
t
PHZ
,
t
PLZ
,
t
PZH
,
t
PZL
5.0
10
15
--
--
--
34
20
15
90
45
35
ns
Crosstalk, Control to Output (V
SS
= 0 Vdc)
(V
C
= V
DD
, R
in
= 10 k
, R
out
= 10 k
,
f = 1.0 kHz)
9
--
5.0
10
15
--
--
--
30
50
100
--
--
--
mV
Crosstalk between any two switches (V
SS
= 0 Vdc)
(R
L
= 1.0 k
, f = 1.0 MHz,
crosstalk
+
20 log10
Vout1
Vout2
)
--
--
5.0
--
80
--
dB
Noise Voltage (V
SS
= 0 Vdc)
(V
C
= V
DD
, f = 100 Hz)
10,11
--
5.0
10
15
--
--
--
24
25
30
--
--
--
nV/
Cycle
(V
C
= V
DD
, f = 100 kHz)
5.0
10
15
--
--
--
12
12
15
--
--
--
Second Harmonic Distortion (V
SS
= 5.0 Vdc)
(V
in
= 1.77 Vdc, RMS Centered @ 0.0 Vdc,
R
L
= 10 k
, f = 1.0 kHz)
--
--
5.0
--
0.16
--
%
Insertion Loss (V
C
= V
DD
, V
in
= 1.77 Vdc,
V
SS
= 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)
Iloss
+
20 log10
Vout
Vin
)
(R
L
= 1.0 k
)
(R
L
= 10 k
)
(R
L
= 100 k
)
(R
L
= 1.0 M
)
12
--
5.0
--
--
--
--
2.3
0.2
0.1
0.05
--
--
--
--
dB
Bandwidth ( 3.0 dB)
(V
C
= V
DD
, V
in
= 1.77 Vdc, V
SS
= 5.0 Vdc,
RMS centered @ 0.0 Vdc)
(R
L
= 1.0 k
)
(R
L
= 10 k
)
(R
L
= 100 k
)
(R
L
= 1.0 M
)
12,13
BW
5.0
--
--
--
--
54
40
38
37
--
--
--
--
MHz
OFF Channel Feedthrough Attenuation
(V
SS
= 5.0 Vdc)
Vout
Vin
+
50 dB)
(R
L
= 1.0 k
)
(R
L
= 10 k
)
(R
L
= 100 k
)
(R
L
= 1.0 M
)
(V
C
= V
SS
, 20 log
10
--
--
5.0
--
--
--
--
1250
140
18
2.0
--
--
--
--
kHz
6. The formulas given are for typical characteristics only at 25
_
C.
7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
MC14016B
http://onsemi.com
5
Figure 1. Input Voltage Test Circuit
V
C
V
in
V
out
I
S
V
IL
: V
C
is raised from V
SS
until V
C
= V
IL
.
V
IL
:
at V
C
= V
IL
: I
S
=
10
A with V
in
= V
SS
, V
out
= V
DD
or V
in
= V
DD
, V
out
= V
SS
.
V
IH
: When V
C
= V
IH
to V
DD
, the switch is ON and the R
ON
specifications are met.
Figure 2. Quiescent Power Dissipation
Test Circuit
Figure 3. Typical Power Dissipation per Circuit
(1/4 of device shown)
PULSE
GENERATOR
V
DD
10 k
I
D
V
DD
V
out
V
SS
V
in
f
c
TO ALL
4 CIRCUITS
P
D
= V
DD
x I
D
50 M
10 M
1.0 M
100 k
10 k
5.0 k
10,000
1000
100
10
1.0
T
A
= 25
C
10 Vdc
5.0 Vdc
f
c
, FREQUENCY (Hz)
, POWER DISSIP
A
TION (
P
D
W)
CONTROL
INPUT
V
DD
= 15 Vdc
TYPICAL R
ON
versus INPUT VOLTAGE
Figure 4. V
SS
= 5.0 V and 7.5 V
Figure 5. V
SS
= 0 V
, "ON" RESIST
ANCE
(OHMS)
R
ON
700
600
500
400
300
200
100
0
10 8.0
4.0
0
4.0
8.0
10
V
in
, INPUT VOLTAGE (Vdc)
, "ON" RESIST
ANCE
(OHMS)
R
ON
700
600
500
400
300
200
100
0
0
2.0
6.0
10
14
18
20
V
in
, INPUT VOLTAGE (Vdc)
R
L
= 10 k
T
A
= 25
C
V
C
= V
DD
= 5.0 Vdc
V
SS
= 5.0 Vdc
V
C
= V
DD
= 7.5 Vdc
V
SS
= 7.5 Vdc
V
SS
= 0 Vdc
R
L
= 10 k
T
A
= 25
C
V
C
= V
DD
= 10 Vdc
V
C
= V
DD
= 15 Vdc
MC14016B
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6
Figure 6. R
ON
Characteristics
Test Circuit
Figure 7. Propagation Delay Test Circuit
and Waveforms
V
C
V
in
V
out
R
L
V
out
V
in
R
L
C
L
20 ns
20 ns
V
DD
V
SS
V
in
V
out
t
PLH
t
PHL
50%
10%
50%
90%
Figure 8. TurnOn Delay Time Test Circuit
and Waveforms
Figure 9. Crosstalk Test Circuit
V
C
V
out
V
in
R
L
C
L
V
X
20 ns
V
C
V
out
V
out
10%
90%
10%
90%
90%
50%
10%
t
PZH
t
PHZ
V
DD
V
SS
t
PLZ
t
PZL
V
in
= V
DD
V
x
= V
SS
V
in
= V
SS
V
x
= V
DD
V
C
V
out
V
in
1 k
10 k
15 pF
Figure 10. Noise Voltage Test Circuit
Figure 11. Typical Noise Characteristics
V
C
= V
DD
OUT
IN
QUANTECH
MODEL
2283
OR EQUIV
100 k
10 k
1.0 k
100
10
35
30
25
20
0
10 Vdc
5.0 Vdc
f, FREQUENCY (Hz)
NOISE VOL
T
AGE (nV/
CYCLE)
15
10
5.0
V
DD
= 15 Vdc
MC14016B
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7
Figure 12. Typical Insertion Loss/Bandwidth
Characteristics
Figure 13. Frequency Response Test Circuit
V
C
V
out
R
L
V
in
+ 2.5 Vdc
0.0 Vdc
2.5 Vdc
100 M
10 M
1.0 M
100 k
10 k
2.0
0
2.0
R
L
= 1 M
AND 100 k
f
in
, INPUT FREQUENCY (Hz)
4.0
6.0
8.0
10
12
TYPICAL
INSER
TION LOSS (dB)
10 k
1.0 k
3.0 dB (R
L
= 1.0 M
)
3.0 dB (R
L
= 10 k
)
3.0 dB (R
L
= 1.0 k
)
Figure 14.
V Across Switch
CONTROL
SECTION
OF IC
SOURCE
V
LOAD
ON SWITCH
MC14016B
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8
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0to5
V Digital Control signal is used to directly control a 5 V
pp
analog signal.
The digital control logic levels are determined by V
DD
and V
SS
. The V
DD
voltage is the logic high voltage; the V
SS
voltage is logic low. For the example, V
DD
= + 5 V logic high
at the control inputs; V
SS
= GND = 0 V logic low.
The maximum analog signal level is determined by V
DD
and V
SS
. The analog voltage must not swing higher than
V
DD
or lower than V
SS
.
The example shows a 5 V
pp
signal which allows no
margin at either peak. If voltage transients above V
DD
and/or below V
SS
are anticipated on the analog channels,
external diodes (D
x
) are recommended as shown in Figure
B. These diodes should be small signal types able to absorb
the maximum anticipated current surges during clipping.
The absolute maximum potential difference between
V
DD
and V
SS
is 18.0 V. Most parameters are specified up to
15 V which is the recommended maximum difference
between V
DD
and V
SS
.
Figure A. Application Example
+ 5 V
V
DD
V
SS
SWITCH
IN
SWITCH
OUT
5 V
pp
ANALOG SIGNAL
0TO5 V DIGITAL
CONTROL SIGNALS
+ 5 V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
5 V
pp
ANALOG SIGNAL
MC14016B
+ 5.0 V
+ 2.5 V
GND
Figure B. External Germanium or Schottky Clipping Diodes
V
DD
V
DD
D
x
D
x
D
x
D
x
V
SS
V
SS
SWITCH
IN
SWITCH
OUT
MC14016B
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9
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE M
1
7
14
8
B
A
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.715
0.770
18.16
18.80
B
0.240
0.260
6.10
6.60
C
0.145
0.185
3.69
4.69
D
0.015
0.021
0.38
0.53
F
0.040
0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052
0.095
1.32
2.41
J
0.008
0.015
0.20
0.38
K
0.115
0.135
2.92
3.43
L
M
10
10
N
0.015
0.039
0.38
1.01
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
H
G
D
K
C
SEATING
PLANE
N
T
14 PL
M
0.13 (0.005)
L
M
J
0.290
0.310
7.37
7.87
MC14016B
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10
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
B
G
P
7 PL
14
8
7
1
M
0.25 (0.010)
B
M
S
B
M
0.25 (0.010)
A
S
T
T
F
R
X 45
SEATING
PLANE
D
14 PL
K
C
J
M
_
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
8.55
8.75
0.337
0.344
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.228
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
MC14016B
http://onsemi.com
11
PACKAGE DIMENSIONS
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96501
ISSUE O
H
E
A
1
DIM
MIN
MAX
MIN
MAX
INCHES
2.05
0.081
MILLIMETERS
0.05
0.20
0.002
0.008
0.35
0.50
0.014
0.020
0.18
0.27
0.007
0.011
9.90
10.50
0.390
0.413
5.10
5.45
0.201
0.215
1.27 BSC
0.050 BSC
7.40
8.20
0.291
0.323
0.50
0.85
0.020
0.033
1.10
1.50
0.043
0.059
0
0.70
0.90
0.028
0.035
1.42
0.056
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
L
E
Q
1
_
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4.
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5.
THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.13 (0.005)
M
0.10 (0.004)
D
Z
E
1
14
8
7
e
A
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
MC14016B
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