www.docs.chipfind.ru
Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 3
1
Publication Order Number:
MC14020B/D
MC14020B
14-Bit Binary Counter
The MC14020B 14stage binary counter is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 14 stages of ripplecarry binary counter. The device
advances the count on the negativegoing edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequencydividing circuits.
Fully Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
Buffered Outputs Available from stages 1 and 4 thru 14
Common Reset Line
PinforPin Replacement for CD4020B
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note NO TAG)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
10
mA
P
D
Power Dissipation,
per Package (Note NO TAG)
500
mW
T
A
Ambient Temperature Range
55 to +125
C
T
stg
Storage Temperature Range
65 to +150
C
T
L
Lead Temperature
(8Second Soldering)
260
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14020BCP
PDIP16
2000/Box
MC14020BD
SOIC16
48/Rail
MC14020BDR2
SOIC16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP16
P SUFFIX
CASE 648
MC14020BCP
AWLYYWW
SOIC16
D SUFFIX
CASE 751B
1
16
14020B
AWLYWW
SOEIAJ16
F SUFFIX
CASE 966
1
16
MC14020B
AWLYWW
TSSOP16
DT SUFFIX
CASE 948F
14
020B
ALYW
1
16
MC14020BDT
TSSOP16
96/Rail
MC14020BF
SOEIAJ16
See Note 1.
MC14020BFEL
SOEIAJ16
See Note 1.
MC14020B
http://onsemi.com
2
TRUTH TABLE
Clock
Reset
Output State
0
No Change
0
Advance to Next State
X
1
All Outputs are Low
X = Don't Care
LOGIC DIAGRAM
CLOCK
RESET
11
10
Q1
Q4
Q5
Q12
Q13
Q14
9
7
5
1
2
3
C
C
R
Q
Q
C
C
R
Q
Q
C
C
R
Q
Q
C
C
R
Q
Q
C
C
R
Q
Q
C
C
Q
R
Q6 = PIN 4
Q7 = PIN 6
Q8 = PIN 13
Q9 = PIN 12
Q10 = PIN 14
Q11 = PIN 15
V
DD
= PIN 16
V
SS
= PIN 8
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
Q9
Q8
Q10
Q11
V
DD
Q1
C
R
Q6
Q14
Q13
Q12
V
SS
Q4
Q7
Q5
MC14020B
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3
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
55
_
C
25
_
C
125
_
C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
Output Voltage
"0" Level
V
in
= V
DD
or 0
V
OL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
"1" Level
V
in
= 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
--
--
--
1.5
3.0
4.0
--
--
--
2.25
4.50
6.75
1.5
3.0
4.0
--
--
--
1.5
3.0
4.0
Vdc
"1" Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
--
--
--
3.5
7.0
11
2.75
5.50
8.25
--
--
--
3.5
7.0
11
--
--
--
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc)
Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
--
--
--
--
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
--
--
--
--
1.7
0.36
0.9
2.4
--
--
--
--
mAdc
(V
OL
= 0.4 Vdc)
Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
--
--
--
0.51
1.3
3.4
0.88
2.25
8.8
--
--
--
0.36
0.9
2.4
--
--
--
mAdc
Input Current
I
in
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
(V
in
= 0)
C
in
--
--
--
--
5.0
7.5
--
--
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
--
--
--
5.0
10
20
--
--
--
0.005
0.010
0.015
5.0
10
20
--
--
--
150
300
600
Adc
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
I
T
= (0.42
A/kHz)f + I
DD
I
T
= (0.85
A/kHz)f + I
DD
I
T
= (1.43
A/kHz)f + I
DD
Adc
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
50) Vfk
where: I
T
is in
A (per package), C
L
in pF, V = (V
DD
V
SS
) in volts, f in kHz is input frequency, and k = 0.001.
MC14020B
http://onsemi.com
4
SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Symbol
V
DD
Vdc
Min
Typ
(8.)
Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
--
--
--
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q1
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 175 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 82 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 55 ns
t
PLH
,
t
PHL
5.0
10
15
--
--
--
260
115
80
520
230
160
ns
Clock to Q14
t
PHL
, t
PLH
(1.7 ns/pF) C
L
+ 1735 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 772 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 535 ns
5.0
10
15
--
--
--
1820
805
560
3900
1725
1200
ns
Propagation Delay Time
Reset to Q
n
t
PHL
= (1.7 ns/pF) C
L
+ 285 ns
t
PHL
= (0.66 ns/pF) C
L
+ 122 ns
t
PHL
= (0.5 ns/pF) C
L
+ 90 ns
t
PHL
5.0
10
15
--
--
--
370
155
115
740
310
230
ns
Clock Pulse Width
t
WH
5.0
10
15
500
165
125
140
55
38
--
--
--
ns
Clock Pulse Frequency
f
cl
5.0
10
15
--
--
--
2.0
6.0
8.0
1.0
3.0
4.0
MHz
Clock Rise and Fall Time
t
TLH
, t
THL
5.0
10
15
No Limit
--
Reset Pulse Width
t
WL
5.0
10
15
3000
550
420
320
120
80
--
--
--
ns
Reset Removal Time
t
rem
5.0
10
15
130
50
30
65
25
15
--
--
--
ns
7. The formulas given are for the typical characteristics only at 25
_
C.
8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
MC14020B
http://onsemi.com
5
Figure 1. Power Dissipation Test Circuit
and Waveform
Figure 2. Switching Time Test Circuit
and Waveforms
500
F
0.01
F
CERAMIC
PULSE
GENERATOR
V
DD
C
L
C
L
C
L
V
SS
C
R
Q1
Q4
Q
n
I
D
V
DD
V
SS
20 ns
20 ns
CLOCK
90%
50%
10%
50% DUTY CYCLE
PULSE
GENERATOR
V
DD
V
SS
C
R
Q1
Q4
Q
n
C
L
C
L
C
L
20 ns
20 ns
CLOCK
90%
50%
10%
t
WH
t
PLH
t
PHL
90%
50%
10%
t
TLH
t
THL
Q
Figure 3. Timing Diagram
CLOCK
RESET
Q1
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
16,384
8192
4096
1
2
4
8
16
32
64
128
256
512
1024
2048
MC14020B
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6
PACKAGE DIMENSIONS
PDIP16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1
8
9
16
K
PLANE
T
M
A
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.740
0.770
18.80
19.55
B
0.250
0.270
6.35
6.85
C
0.145
0.175
3.69
4.44
D
0.015
0.021
0.39
0.53
F
0.040
0.70
1.02
1.77
G
0.100 BSC
2.54 BSC
H
0.050 BSC
1.27 BSC
J
0.008
0.015
0.21
0.38
K
0.110
0.130
2.80
3.30
L
0.295
0.305
7.50
7.74
M
0
10
0
10
S
0.020
0.040
0.51
1.01
_
_
_
_
SOIC16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
16
9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PL
P
B
A
M
0.25 (0.010)
B
S
T
D
K
C
16 PL
S
B
M
0.25 (0.010)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
MC14020B
http://onsemi.com
7
PACKAGE DIMENSIONS
TSSOP16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F01
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
1.20
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.18
0.28
0.007
0.011
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0
8
0
8
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4.
DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5.
DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6.
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7.
DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
_
_
_
_
SECTION NN
SEATING
PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X
L/2
U
S
U
0.15 (0.006) T
S
U
0.15 (0.006) T
S
U
M
0.10 (0.004)
V
S
T
0.10 (0.004)
T
V
W
0.25 (0.010)
16X REF
K
N
N
MC14020B
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8
PACKAGE DIMENSIONS
H
E
A
1
DIM
MIN
MAX
MIN
MAX
INCHES
2.05
0.081
MILLIMETERS
0.05
0.20
0.002
0.008
0.35
0.50
0.014
0.020
0.18
0.27
0.007
0.011
9.90
10.50
0.390
0.413
5.10
5.45
0.201
0.215
1.27 BSC
0.050 BSC
7.40
8.20
0.291
0.323
0.50
0.85
0.020
0.033
1.10
1.50
0.043
0.059
0
0.70
0.90
0.028
0.035
0.78
0.031
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
L
E
Q
1
_
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4.
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5.
THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005)
0.10 (0.004)
1
16
9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
SOEIAJ16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96601
ISSUE O
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
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PUBLICATION ORDERING INFORMATION
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ON Semiconductor Website: http://onsemi.com
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Sales Representative.
MC14020B/D
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Email: ONlit@hibbertco.com
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