Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 3
1
Publication Order Number:
MC14040B/D
MC14040B
12-Bit Binary Counter
The MC14040B 12stage binary counter is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripplecarry binary counter. The device
advances the count on the negativegoing edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequencydriving circuits.
Fully Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
Common Reset Line
PinforPin Replacement for CD4040B
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Ambient Temperature Range
55 to +125
C
T
stg
Storage Temperature Range
65 to +150
C
T
L
Lead Temperature
(8Second Soldering)
260
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
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A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14040BCP
PDIP16
2000/Box
MC14040BD
SOIC16
2400/Box
MC14040BDR2
SOIC16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP16
P SUFFIX
CASE 648
MC14040BCP
AWLYYWW
SOIC16
D SUFFIX
CASE 751B
1
16
14040B
AWLYWW
SOEIAJ16
F SUFFIX
CASE 966
1
16
MC14040B
AWLYWW
MC14040BDT
TSSOP16
96/Rail
MC14040BF
SOEIAJ16
See Note 1.
MC14040BFEL
SOEIAJ16
See Note 1.
TSSOP16
DT SUFFIX
CASE 948F
14
040B
ALYW
1
16
MC14040B
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3
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
55
_
C
25
_
C
125
_
C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
Output Voltage
"0" Level
V
in
= V
DD
or 0
V
OL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
"1" Level
V
in
= 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
--
--
--
1.5
3.0
4.0
--
--
--
2.25
4.50
6.75
1.5
3.0
4.0
--
--
--
1.5
3.0
4.0
Vdc
"1" Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
--
--
--
3.5
7.0
11
2.75
5.50
8.25
--
--
--
3.5
7.0
11
--
--
--
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc)
Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
--
--
--
--
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
--
--
--
--
1.7
0.36
0.9
2.4
--
--
--
--
mAdc
(V
OL
= 0.4 Vdc)
Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
--
--
--
0.51
1.3
3.4
0.88
2.25
8.8
--
--
--
0.36
0.9
2.4
--
--
--
mAdc
Input Current
I
in
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
(V
in
= 0)
C
in
--
--
--
--
5.0
7.5
--
--
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
--
--
--
5.0
10
20
--
--
--
0.005
0.010
0.015
5.0
10
20
--
--
--
150
300
600
Adc
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
I
T
= (0.42
A/kHz) f + I
DD
I
T
= (0.85
A/kHz) f + I
DD
I
T
= (1.43
A/kHz) f + I
DD
Adc
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
50) Vfk
where: I
T
is in
A (per package), C
L
in pF, V = (V
DD
V
SS
) in volts, f in kHz is input frequency, and k = 0.001.
MC14040B
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4
SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Symbol
V
DD
Vdc
Min
Typ
(8.)
Max
Unit
Output Rise and Fall Time
T
TLH
, T
THL
= (1.5 ns/pF) C
L
+ 25 ns
T
TLH
, T
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
T
TLH
, T
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
--
--
--
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q1
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 315 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 137 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 95 ns
t
PLH
,
t
PHL
5.0
10
15
--
--
--
260
115
80
520
230
160
ns
Clock to Q12
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 2415 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 867 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 475 ns
5.0
10
15
--
--
--
1625
720
500
3250
1440
1000
ns
Propagation Delay Time
Reset to Q
n
t
PHL
= (1.7 ns/pF) C
L
+ 485 ns
t
PHL
= (0.86 ns/pF) C
L
+ 182 ns
t
PHL
= (0.5 ns/pF) C
L
+ 145 ns
t
PHL
5.0
10
15
--
--
--
370
155
115
740
310
230
ns
Clock Pulse Width
t
WH
5.0
10
15
385
150
115
140
55
38
--
--
--
ns
Clock Pulse Frequency
f
cl
5.0
10
15
--
--
--
2.1
7.0
10.0
1.5
3.5
4.5
MHz
Clock Rise and Fall Time
t
TLH
, t
THL
5.0
10
15
No Limit
ns
Reset Pulse Width
t
WH
5.0
10
15
960
360
270
320
120
80
--
--
--
ns
Reset Removal Time
t
rem
5.0
10
15
130
50
30
65
25
15
--
--
--
ns
7. The formulas given are for the typical characteristics only at 25
_
C.
8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
Figure 1. Power Dissipation Test Circuit
and Waveform
Figure 2. Switching Time Test Circuit
and Waveforms
PULSE
GENERATOR
PULSE
GENERATOR
500
F
0.01
F
CERAMIC
V
DD
V
SS
C
L
C
L
C
L
I
D
Q1
Q2
Q
n
C
R
20 ns
20 ns
V
DD
V
SS
90%
50%
10%
CLOCK
50% DUTY CYCLE
V
DD
V
SS
C
L
C
L
C
L
Q1
Q2
Q
n
C
R
20 ns
20 ns
CLOCK
90%
50%
10%
t
WH
t
PHL
t
PLH
Q
90%
50%
10%
t
TLH
t
THL
MC14040B
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5
Figure 3. Timing Diagram
CLOCK
RESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
APPLICATIONS INFORMATION
TIMEBASE GENERATOR
A 60 Hz sinewave obtained through a 1.0 Megohm
resistor connected directly to a standard 120 Vac power line
is applied to the clock input of the MC14040B. By selecting
outputs Q5, Q10, Q11, and Q12 division by 3600 is
accomplished. The MC14012B decodes the counter
outputs, produces a single output pulse, and resets the binary
counter. The resulting output frequency is 1.0 pulse/minute.
V
DD
V
SS
120 Vac
60 Hz
1.0 M
20 pF
MC14040B
C
R
Q12
Q11
Q10
Q5
1/2
MC14012B
1/2
MC14012B
1.0 PULSE/MINUTE
OUTPUT
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