Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 3
1
Publication Order Number:
MC14049UB/D
MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logiclevel conversion using only one
supply voltage, V
DD
. The inputsignal high level (V
IH
) can exceed the
V
DD
supply voltage for logiclevel conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOStoTTL/DTL
converters (V
DD
= 5.0 V, V
OL
v 0.4 V, I
OL
3.2 mA). Note that pins
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
High Source and Sink Currents
HightoLow Level Converter
Supply Voltage Range = 3.0 V to 18 V
Meets JEDEC UB Specifications
V
IN
can exceed V
DD
Improved ESD Protection on All Inputs
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
Input Voltage Range
(DC or Transient)
0.5 to +18.0
V
V
out
Output Voltage Range
(DC or Transient)
0.5 to V
DD
+0.5
V
I
in
Input Current
(DC or Transient) per Pin
10
mA
I
out
Output Current
(DC or Transient) per Pin
+45
mA
P
D
Power Dissipation,
per Package (Note 3.)
Plastic
SOIC
825
740
mW
T
A
Ambient Temperature Range
55 to +125
C
T
stg
Storage Temperature Range
65 to +150
C
T
L
Lead Temperature
(8Second Soldering)
260
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the V
SS
pin, only. Extra precautions
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this highimpedance circuit. For proper operation, the ranges V
SS
v
V
in
v
18 V and V
SS
v
V
out
v
V
DD
are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
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A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14049UBCP
PDIP16
2000/Box
MC14049UBD
SOIC16
2400/Box
MC14049UBDR2
SOIC16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP16
P SUFFIX
CASE 648
MC14049UBCP
AWLYYWW
SOIC16
D SUFFIX
CASE 751B
1
16
14049U
AWLYWW
SOEIAJ16
F SUFFIX
CASE 966
1
16
MC14049U
AWLYWW
MC14049UBDT
TSSOP16
96/Rail
MC14049UBDTR2 TSSOP16 2500/Tape & Reel
MC14049UBF
SOEIAJ16
See Note 1.
MC14049UBFEL
SOEIAJ16
See Note 1.
TSSOP16
DT SUFFIX
CASE 948F
14
049U
ALYW
1
16
MC14049UB
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2
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
OUT
E
NC
IN
F
OUT
F
NC
IN
D
OUT
D
IN
E
OUT
B
IN
A
OUT
A
V
DD
V
SS
IN
C
OUT
C
IN
B
NC = NO CONNECTION
LOGIC DIAGRAM
MC14049UB
14
15
11
9
7
5
3
12
10
6
4
2
NC = PIN 13, 16
V
SS
= PIN 8
V
DD
= PIN 1
CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
V
DD
V
SS
MC14049UB
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
55
_
C
25
_
C
125
_
C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
Output Voltage
"0" Level
V
in
= V
DD
or 0
V
OL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
"1" Level
V
in
= 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(V
O
= 4.5 Vdc)
(V
O
= 9.0 Vdc)
(V
O
= 13.5 Vdc)
V
IL
5.0
10
15
--
--
--
1.0
2.0
2.5
--
--
--
2.25
4.50
6.75
1.0
2.0
2.5
--
--
--
1.0
2.0
2.5
Vdc
"1" Level
(V
O
= 0.5 Vdc)
(V
O
= 1.0 Vdc)
(V
O
= 1.5 Vdc)
V
IH
5.0
10
15
4.0
8.0
12.5
--
--
--
4.0
8.0
12.5
2.75
5.50
8.25
--
--
--
4.0
8.0
12.5
--
--
--
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc)
Source
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
10
15
1.6
1.6
4.7
--
--
--
1.25
1.3
3.75
2.5
2.6
10
--
--
--
1.0
1.0
3.0
--
--
--
mAdc
(V
OL
= 0.4 Vdc)
Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
3.75
10
30
--
--
--
3.2
8.0
24
6.0
16
40
--
--
--
2.6
6.6
19
--
--
--
mAdc
Input Current
I
in
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance (V
in
= 0)
C
in
--
--
--
--
10
20
--
--
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
--
--
--
1.0
2.0
4.0
--
--
--
0.002
0.004
0.006
1.0
2.0
4.0
--
--
--
30
60
120
Adc
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
I
T
= (1.8
A/kHz) f + I
DD
I
T
= (3.5
A/kHz) f + I
DD
I
T
= (5.3
A/kHz) f + I
DD
Adc
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
50) Vfk
where: I
T
is in
A (per package), C
L
in pF, V = (V
DD
V
SS
) in volts, f in kHz is input frequency, and k = 0.002.
MC14049UB
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4
Figure 2. Typical Output Source Characteristics
Figure 3. Typical Output Sink Characteristics
V
DD
V
SS
1
8
I
OH
V
OH
V
DS
= V
OH
V
DD
V
DD
V
SS
1
8
I
OL
V
OL
V
DD
= V
OL
I OH
,
OUT
P
UT
SOU
R
CE
CU
RR
NT
(m
A
dc)
I OL
,
OUTPUT
SINK CURRENT
(mAdc)
50
40
30
20
10
0
10
8.0
6.0
4.0
2.0
0
V
DS
, DRAINTOSOURCE VOLTAGE (Vdc)
V
GS
= 5.0 Vdc
V
GS
= 10 Vdc
MAXIMUM CURRENT LEVEL
V
GS
= 15 Vdc
160
120
80
40
0
0
2.0
4.0
6.0
8.0
10
V
DS
, DRAINTOSOURCE VOLTAGE (Vdc)
V
GS
= 15 Vdc
V
GS
= 10 Vdc
MAXIMUM CURRENT LEVEL
V
GS
= 5.0 Vdc
Figure 4. Ambient Temperature Power Derating
P
D
, M
A
X
I
M
U
M P
O
W
E
R
DISSI
P
A
TION
(mW)
PER P
ACKAGE
1200
1100
1000
900
825
800
740
700
600
500
400
300
200
100
0
175
150
125
100
75
50
25
T
A
, AMBIENT TEMPERATURE (
C)
175 mW (P)
120 mW (D)
(P) PDIP
(D) SOIC
PULSE
GENERATOR
V
DD
V
SS
8
1
C
L
V
out
V
in
20 ns
20 ns
V
DD
V
SS
V
OH
V
OL
90%
50%
10%
90%
50%
10%
t
PLH
t
TLH
t
THL
t
PHL
OUTPUT
INPUT
Figure 5. Switching Time Test Circuit
and Waveforms
MC14049UB
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5
PACKAGE DIMENSIONS
PDIP16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1
8
9
16
K
PLANE
T
M
A
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.740
0.770
18.80
19.55
B
0.250
0.270
6.35
6.85
C
0.145
0.175
3.69
4.44
D
0.015
0.021
0.39
0.53
F
0.040
0.70
1.02
1.77
G
0.100 BSC
2.54 BSC
H
0.050 BSC
1.27 BSC
J
0.008
0.015
0.21
0.38
K
0.110
0.130
2.80
3.30
L
0.295
0.305
7.50
7.74
M
0
10
0
10
S
0.020
0.040
0.51
1.01
_
_
_
_
SOIC16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
16
9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PL
P
B
A
M
0.25 (0.010)
B
S
T
D
K
C
16 PL
S
B
M
0.25 (0.010)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
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