Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 3
1
Publication Order Number:
MC14051B/D
MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitallycontrolled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
Triple Diode Protection on Control Inputs
Switch Function is Break Before Make
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Analog Voltage Range (V
DD
V
EE
) = 3.0 to 18 V
Note: V
EE
must be
v V
SS
Linearized Transfer Characteristics
Lownoise 12 nV/
Cycle, f
1.0 kHz Typical
PinforPin Replacement for CD4051, CD4052, and CD4053
For 4PDT Switch, See MC14551B
For Lower R
ON
, Use the HC4051, HC4052, or HC4053 HighSpeed
CMOS Devices
MAXIMUM RATINGS
(Note 1.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage (Referenced
to V
EE
, V
SS
V
EE
)
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient) (Referen
ced to V
SS
for Control Inputs
and V
EE
for Switch I/O)
0.5 to V
DD
+ 0.5
V
I
in
Input Current (DC or Transient)
per Control Pin
10
mA
I
SW
Switch Through Current
25
mA
P
D
Power Dissipation,
per Package (Note 2.)
500
mW
T
A
Ambient Temperature Range
55 to +125
C
T
stg
Storage Temperature Range
65 to +150
C
T
L
Lead Temperature
(8Second Soldering)
260
C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
, V
EE
or V
DD
). Unused outputs must be left open.
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XX
= Specific Device Code
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
MARKING
DIAGRAMS
1
16
PDIP16
P SUFFIX
CASE 648
MC140XXBCP
AWLYYWW
SOIC16
D SUFFIX
CASE 751B
1
16
140XXB
AWLYWW
SOEIAJ16
F SUFFIX
CASE 966
1
16
MC140XXB
AWLYWW
TSSOP16
DT SUFFIX
CASE 948F
14
0XXB
ALYW
1
16
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
ORDERING INFORMATION
MC14051B, MC14052B, MC14053B
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2
MC14051B
8Channel Analog
Multiplexer/Demultiplexer
MC14052B
Dual 4Channel Analog
Multiplexer/Demultiplexer
MC14053B
Triple 2Channel Analog
Multiplexer/Demultiplexer
V
DD
= PIN 16
V
SS
= PIN 8
V
EE
= PIN 7
Note: Control Inputs referenced to V
SS
, Analog Inputs and Outputs reference to V
EE
. V
EE
must be
V
SS
.
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
X
4
2
5
1
12
15
14
13
9
10
11
6
CONTROLS
SWITCHES
IN/OUT
COMMON
OUT/IN
3
4
2
5
1
11
15
14
12
9
10
6
CONTROLS
SWITCHES
IN/OUT
13
3
COMMONS
OUT/IN
X
Y
V
DD
= PIN 16
V
SS
= PIN 8
V
EE
= PIN 7
3
5
1
2
13
12
9
10
11
6
CONTROLS
SWITCHES
IN/OUT
14
15
4
X
Y
Z
COMMONS
OUT/IN
V
DD
= PIN 16
V
SS
= PIN 8
V
EE
= PIN 7
INHIBIT
A
B
X0
X1
X2
X3
Y0
Y1
Y2
Y3
INHIBIT
A
B
C
X0
Y0
Y1
Z0
Z1
X1
PIN ASSIGMENT
MC14051B
MC14052B
MC14053B
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
X3
X0
X1
X2
V
DD
C
B
A
X7
X
X6
X4
V
SS
V
EE
INH
X5
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
X0
X
X1
X2
V
DD
B
A
X3
Y3
Y
Y2
Y0
V
SS
V
EE
INH
Y1
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
X0
X1
X
Y
V
DD
C
B
A
Z
Z1
Y0
Y1
V
SS
V
EE
INH
Z0
MC14051B, MC14052B, MC14053B
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3
ELECTRICAL CHARACTERISTICS
55
_
C
25
_
C
125
_
C
Characteristic
Symbol
V
DD
Test Conditions
Min
Max
Min
Typ
(3.)
Max
Min
Max
Unit
SUPPLY REQUIREMENTS (Voltages Referenced to V
EE
)
Power Supply Voltage
Range
V
DD
--
V
DD
3.0
V
SS
V
EE
3.0
18
3.0
--
18
3.0
18
V
Quiescent Current Per
Package
I
DD
5.0
10
15
Control Inputs:
V
in
= V
SS
or V
DD
,
Switch I/O: V
EE
v
V
I/O
v
V
DD
, and
V
switch
v
500 mV
(4.)
--
--
--
5.0
10
20
--
--
--
0.005
0.010
0.015
5.0
10
20
--
--
--
150
300
600
A
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
I
D(AV)
5.0
10
15
T
A
= 25
_
C only (The
channel component,
(V
in
V
out
)/R
on
, is
not included.)
(0.07
A/kHz) f + I
DD
Typical
(0.20
A/kHz) f + I
DD
(0.36
A/kHz) f + I
DD
A
CONTROL INPUTS -- INHIBIT, A, B, C (Voltages Referenced to V
SS
)
LowLevel Input Voltage
V
IL
5.0
10
15
R
on
= per spec,
I
off
= per spec
--
--
--
1.5
3.0
4.0
--
--
--
2.25
4.50
6.75
1.5
3.0
4.0
--
--
--
1.5
3.0
4.0
V
HighLevel Input Voltage
V
IH
5.0
10
15
R
on
= per spec,
I
off
= per spec
3.5
7.0
11
--
--
--
3.5
7.0
11
2.75
5.50
8.25
--
--
--
3.5
7.0
11
--
--
--
V
Input Leakage Current
I
in
15
V
in
= 0 or V
DD
--
0.1
--
0.00001
0.1
--
1.0
A
Input Capacitance
C
in
--
--
--
--
5.0
7.5
--
--
pF
SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to V
EE
)
Recommended
PeaktoPeak Voltage
Into or Out of the Switch
V
I/O
--
Channel On or Off
0
V
DD
0
--
V
DD
0
V
DD
V
PP
Recommended Static or
Dynamic Voltage Across
the Switch
(4.)
(Figure 5)
V
switch
--
Channel On
0
600
0
--
600
0
300
mV
Output Offset Voltage
V
OO
--
V
in
= 0 V, No Load
--
--
--
10
--
--
--
V
ON Resistance
R
on
5.0
10
15
V
switch
v
500 mV
(4.)
V
in
= V
IL
or V
IH
(Control), and V
in
=
0 to V
DD
(Switch)
--
--
--
800
400
220
--
--
--
250
120
80
1050
500
280
--
--
--
1200
520
300
ON Resistance Between
Any Two Channels in the
Same Package
R
on
5.0
10
15
--
--
--
70
50
45
--
--
--
25
10
10
70
50
45
--
--
--
135
95
65
OffChannel Leakage
Current (Figure 10)
I
off
15
V
in
= V
IL
or V
IH
(Control) Channel to
Channel or Any One
Channel
--
100
--
0.05
100
--
1000
nA
Capacitance, Switch I/O
C
I/O
--
Inhibit = V
DD
--
--
--
10
--
--
--
pF
Capacitance, Common O/I
C
O/I
--
Inhibit = V
DD
(MC14051B)
(MC14052B)
(MC14053B)
--
--
--
--
--
--
--
--
--
60
32
17
--
--
--
--
--
--
--
--
--
pF
Capacitance, Feedthrough
(Channel Off)
C
I/O
--
--
Pins Not Adjacent
Pins Adjacent
--
--
--
--
--
--
0.15
0.47
--
--
--
--
--
--
pF
3. Data labeled "Typ" is not to be used for design purposes, but is intended as an indication of the IC's potential performance.
4. For voltage drops across the switch (
V
switch
) > 600 mV ( > 300 mV at high temperature), excessive V
DD
current may be drawn, i.e. the
current out of the switch may contain both V
DD
and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
MC14051B, MC14052B, MC14053B
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4
ELECTRICAL CHARACTERISTICS
(5.)
(C
L
= 50 pF, T
A
= 25
_
C) (V
EE
v
V
SS
unless otherwise indicated)
Characteristic
Symbol
V
DD
V
EE
Vdc
Typ
(6.)
All Types
Max
Unit
Propagation Delay Times (Figure 6)
Switch Input to Switch Output (R
L
= 10 k
)
MC14051
t
PLH
, t
PHL
= (0.17 ns/pF) C
L
+ 26.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) C
L
+ 11 ns
t
PLH
, t
PHL
= (0.06 ns/pF) C
L
+ 9.0 ns
t
PLH
, t
PHL
5.0
10
15
35
15
12
90
40
30
ns
MC14052
t
PLH
, t
PHL
= (0.17 ns/pF) C
L
+ 21.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) C
L
+ 8.0 ns
t
PLH
, t
PHL
= (0.06 ns/pF) C
L
+ 7.0 ns
5.0
10
15
30
12
10
75
30
25
ns
MC14053
t
PLH
, t
PHL
= (0.17 ns/pF) C
L
+ 16.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) C
L
+ 4.0 ns
t
PLH
, t
PHL
= (0.06 ns/pF) C
L
+ 3.0 ns
5.0
10
15
25
8.0
6.0
65
20
15
ns
Inhibit to Output (R
L
= 10 k
, V
EE
= V
SS
)
Output "1" or "0" to High Impedance, or
High Impedance to "1" or "0" Level
MC14051B
t
PHZ
, t
PLZ
,
t
PZH
, t
PZL
5.0
10
15
350
170
140
700
340
280
ns
MC14052B
5.0
10
15
300
155
125
600
310
250
ns
MC14053B
5.0
10
15
275
140
110
550
280
220
ns
Control Input to Output (R
L
= 10 k
, V
EE
= V
SS
)
MC14051B
t
PLH
, t
PHL
5.0
10
15
360
160
120
720
320
240
ns
MC14052B
5.0
10
15
325
130
90
650
260
180
ns
MC14053B
5.0
10
15
300
120
80
600
240
160
ns
Second Harmonic Distortion
(R
L
= 10K
, f = 1 kHz) V
in
= 5 V
PP
--
10
0.07
--
%
Bandwidth (Figure 7)
(R
L
= 1 k
, V
in
= 1/2 (V
DD
V
EE
) pp, C
L
= 50pF
20 Log (V
out
/V
in
) = 3 dB)
BW
10
17
--
MHz
Off Channel Feedthrough Attenuation (Figure 7)
R
L
= 1K
, V
in
= 1/2 (V
DD
V
EE
) pp
f
in
= 4.5 MHz -- MC14051B
f
in
= 30 MHz -- MC14052B
f
in
= 55 MHz -- MC14053B
--
10
50
--
dB
Channel Separation (Figure 8)
(R
L
= 1 k
, V
in
= 1/2 (V
DD
V
EE
) pp,
f
in
= 3.0 MHz
--
10
50
--
dB
Crosstalk, Control Input to Common O/I (Figure 9)
(R
1
= 1 k
, R
L
= 10 k
Control t
TLH
= t
THL
= 20 ns, Inhibit = V
SS
)
--
10
75
--
mV
5. The formulas given are for the typical characteristics only at 25
_
C.
6. Data labelled "Typ" is not lo be used for design purposes but In intended as an indication of the IC's potential performance.
MC14051B, MC14052B, MC14053B
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5
Figure 1. Switch Circuit Schematic
IN/OUT
LEVEL
CONVERTED
CONTROL
V
DD
V
EE
V
DD
V
DD
V
DD
OUT/IN
V
EE
IN/OUT
OUT/IN
CONTROL
TRUTH TABLE
Control Inputs
Select
ON Switches
Inhibit
C*
B
A
MC14051B
MC14052B
MC14053B
0
0
0
0
X0
Y0
X0
Z0
Y0
X0
0
0
0
1
X1
Y1
X1
Z0
Y0
X1
0
0
1
0
X2
Y2
X2
Z0
Y1
X0
0
0
1
1
X3
Y3
X3
Z0
Y1
X1
0
1
0
0
X4
Z1
Y0
X0
0
1
0
1
X5
Z1
Y0
X1
0
1
1
0
X6
Z1
Y1
X0
0
1
1
1
X7
Z1
Y1
X1
1
x
x
x
None
None
None
*Not applicable for MC14052
x = Don't Care
Figure 3. MC14052B Functional Diagram
Figure 4. MC14053B Functional Diagram
16
V
DD
8
V
SS
7
V
EE
13 X
3 Y
BINARY TO 1OF4
DECODER WITH
INHIBIT
LEVEL
CONVERTER
INH 6
A 10
B 9
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
BINARY TO 1OF2
DECODER WITH
INHIBIT
LEVEL
CONVERTER
16
V
DD
8
V
SS
7
V
EE
14 X
15 Y
4 Z
INH 6
A 11
B 10
C 9
X0 12
X1 13
Y0 2
Y1 1
Z0 5
Z1 3
Figure 2. MC14051B Functional Diagram
INH 6
A 11
B 10
C 9
X0 13
X1 14
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4
8
V
SS
7
V
EE
16
V
DD
3 X
BINARY TO 1OF8
DECODER WITH
INHIBIT
LEVEL
CONVERTER
MC14051B, MC14052B, MC14053B
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6
TEST CIRCUITS
Figure 5.
V Across Switch
Figure 6. Propagation Delay Times,
Control and Inhibit to Output
Figure 7. Bandwidth and OffChannel
Feedthrough Attenuation
Figure 8. Channel Separation
(Adjacent Channels Used For Setup)
Figure 9. Crosstalk, Control Input to
Common O/I
Figure 10. Off Channel Leakage
CONTROL
SECTION
OF IC
SOURCE
V
ON SWITCH
PULSE
GENERATOR
INH
A
B
C
R
L
C
L
V
out
V
DD
V
EE
V
EE
V
DD
INH
A
B
C
V
SS
V
in
R
L
C
L
= 50 pF
V
out
V
DD
V
EE
2
INH
A
B
C
OFF
ON
R
L
R
L
C
L
= 50 pF
V
out
V
in
V
DD
V
EE
2
INH
A
B
C
R1
R
L
C
L
= 50 pF
V
out
CONTROL
SECTION
OF IC
OFF CHANNEL UNDER TEST
OTHER
CHANNEL(S)
COMMON
V
DD
V
EE
V
EE
V
DD
V
EE
V
DD
NOTE: See also Figures 7 and 8 in the MC14016B
data sheet.
A, B, and C inputs used to turn ON
or OFF
the switch under test.
LOAD
MC14051B, MC14052B, MC14053B
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7
Figure 11. Channel Resistance (R
ON
) Test Circuit
V
DD
V
EE
= V
SS
10 k
V
DD
KEITHLEY 160
DIGITAL
MULTIMETER
1 k
RANGE
XY
PLOTTER
TYPICAL RESISTANCE CHARACTERISTICS
Figure 12. V
DD
= 7.5 V, V
EE
= 7.5 V
Figure 13. V
DD
= 5.0 V, V
EE
= 5.0 V
R
ON
, "ON" RESIST
ANCE
(OHMS)
350
300
250
200
150
100
0
50
8.0
10
6.0 4.0 2.0
0
0.2
4.0
6.0
8.0
10
V
in
, INPUT VOLTAGE (VOLTS)
T
A
= 125
C
25
C
55
C
R
ON
, "ON" RESIST
ANCE
(OHMS)
350
300
250
200
150
100
0
50
8.0
10
6.0 4.0 2.0
0
0.2
4.0
6.0
8.0
10
V
in
, INPUT VOLTAGE (VOLTS)
T
A
= 125
C
25
C
55
C
Figure 14. V
DD
= 2.5 V, V
EE
= 2.5 V
R
ON
, "ON" RESIST
ANCE
(OHMS)
700
600
500
400
300
200
0
100
8.0
10
6.0 4.0 2.0
0
0.2
4.0
6.0
8.0
10
V
in
, INPUT VOLTAGE (VOLTS)
T
A
= 125
C
25
C
55
C
Figure 15. Comparison at 25
C, V
DD
= V
EE
R
ON
, "ON" RESIST
ANCE
(OHMS)
350
300
250
200
150
100
0
50
8.0
10
6.0 4.0 2.0
0
0.2
4.0
6.0
8.0
10
V
in
, INPUT VOLTAGE (VOLTS)
T
A
= 25
C
V
DD
= 2.5 V
5.0 V
7.5 V
MC14051B, MC14052B, MC14053B
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8
APPLICATIONS INFORMATION
Figure A illustrates use of the onchip level converter
detailed in Figures 2, 3, and 4. The 0to5 V Digital Control
signal is used to directly control a 9 V
pp
analog signal.
The digital control logic levels are determined by V
DD
and V
SS
. The V
DD
voltage is the logic high voltage; the V
SS
voltage is logic low. For the example, V
DD
= + 5 V = logic
high at the control inputs; V
SS
= GND = 0 V = logic low.
The maximum analog signal level is determined by V
DD
and V
EE
. The V
DD
voltage determines the maximum
recommended peak above V
SS
. The V
EE
voltage
determines the maximum swing below V
SS
. For the
example, V
DD
V
SS
= 5 V maximum swing above V
SS
;
V
SS
V
EE
= 5 V maximum swing below V
SS
. The example
shows a
4.5 V signal which allows a 1/2 volt margin at each
peak. If voltage transients above V
DD
and/or below V
EE
are
anticipated on the analog channels, external diodes (Dx) are
recommended as shown in Figure B. These diodes should be
small signal types able to absorb the maximum anticipated
current surges during clipping.
The absolute maximum potential difference between
V
DD
and V
EE
is 18.0 V. Most parameters are specified up to
15 V which is the recommended maximum difference
between V
DD
and V
EE
.
Balanced supplies are not required. However, V
SS
must
be greater than or equal to V
EE
. For example, V
DD
= + 10
V, V
SS
= + 5 V, and V
EE
3 V is acceptable. See the Table
below.
Figure A. Application Example
+ 5 V
5 V
V
DD
V
SS
V
EE
9 V
pp
ANALOG SIGNAL
0TO5 V DIGITAL
CONTROL SIGNALS
SWITCH
I/O
INHIBIT,
A, B, C
COMMON
O/I
9 V
pp
ANALOG SIGNAL
+
4.5 V
4.5 V
GND
+ 5 V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
MC14051B
MC14052B
MC14053B
Figure B. External Germanium or Schottky Clipping Diodes
V
DD
V
DD
V
EE
V
EE
D
X
D
X
D
X
D
X
ANALOG
I/O
COMMON
O/I
POSSIBLE SUPPLY CONNECTIONS
V
DD
In Volts
V
SS
In Volts
V
EE
In Volts
Control Inputs
Logic High/Logic Low
In Volts
Maximum Analog Signal Range
In Volts
+ 8
0
8
+ 8/0
+ 8 to 8 = 16 V
pp
+ 5
0
12
+ 5/0
+ 5 to 12 = 17 V
pp
+ 5
0
0
+ 5/0
+ 5 to 0 = 5 V
pp
+ 5
0
5
+ 5/0
+ 5 to 5 = 10 V
pp
+ 10
+ 5
5
+ 10/ + 5
+ 10 to 5 = 15 V
pp
MC14051B, MC14052B, MC14053B
http://onsemi.com
9
PACKAGE DIMENSIONS
PDIP16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1
8
9
16
K
PLANE
T
M
A
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.740
0.770
18.80
19.55
B
0.250
0.270
6.35
6.85
C
0.145
0.175
3.69
4.44
D
0.015
0.021
0.39
0.53
F
0.040
0.70
1.02
1.77
G
0.100 BSC
2.54 BSC
H
0.050 BSC
1.27 BSC
J
0.008
0.015
0.21
0.38
K
0.110
0.130
2.80
3.30
L
0.295
0.305
7.50
7.74
M
0
10
0
10
S
0.020
0.040
0.51
1.01
_
_
_
_
SOIC16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
16
9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PL
P
B
A
M
0.25 (0.010)
B
S
T
D
K
C
16 PL
S
B
M
0.25 (0.010)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
MC14051B, MC14052B, MC14053B
http://onsemi.com
10
PACKAGE DIMENSIONS
TSSOP16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F01
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
1.20
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.18
0.28
0.007
0.011
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0
8
0
8
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4.
DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5.
DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6.
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7.
DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
_
_
_
_
SECTION NN
SEATING
PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X
L/2
U
S
U
0.15 (0.006) T
S
U
0.15 (0.006) T
S
U
M
0.10 (0.004)
V
S
T
0.10 (0.004)
T
V
W
0.25 (0.010)
16X REF
K
N
N
MC14051B, MC14052B, MC14053B
http://onsemi.com
11
PACKAGE DIMENSIONS
H
E
A
1
DIM
MIN
MAX
MIN
MAX
INCHES
2.05
0.081
MILLIMETERS
0.05
0.20
0.002
0.008
0.35
0.50
0.014
0.020
0.18
0.27
0.007
0.011
9.90
10.50
0.390
0.413
5.10
5.45
0.201
0.215
1.27 BSC
0.050 BSC
7.40
8.20
0.291
0.323
0.50
0.85
0.020
0.033
1.10
1.50
0.043
0.059
0
0.70
0.90
0.028
0.035
0.78
0.031
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
L
E
Q
1
_
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4.
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5.
THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005)
0.10 (0.004)
1
16
9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
SOEIAJ16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96601
ISSUE O
MC14051B, MC14052B, MC14053B
http://onsemi.com
12
ORDERING & SHIPPING INFORMATION:
Device
Package
Shipping
MC14051BCP
PDIP16
2000 Units per Box
MC14051BD
SOIC16
48 Units per Rail
MC14051BDR2
SOIC16
2500 Units / Tape & Reel
MC14051BDT
TSSOP16
96 Units per Rail
MC14051BDTEL
TSSOP16
2000 Units / Tape & Reel
MC14051BDTR2
TSSOP16
2500 Units / Tape & Reel
MC14051BF
SOEIAJ16
See Note 7.
MC14051BFEL
SOEIAJ16
See Note 7.
MC14052BCP
PDIP16
2000 Units per Box
MC14052BD
SOIC16
48 Units per Rail
MC14052BDR2
SOIC16
2500 Units / Tape & Reel
MC14052BDT
TSSOP16
96 Units per Rail
MC14052BDTR2
TSSOP16
2500 Units / Tape & Reel
MC14052BF
SOEIAJ16
See Note 7.
MC14052BFEL
SOEIAJ16
See Note 7.
ORDERING & SHIPPING INFORMATION:
MC14053BCP
PDIP16
2000 Units per Box
MC14053BD
SOIC16
48 Units per Rail
MC14053BDR2
SOIC16
2500 Units / Tape & Reel
MC14053BDT
TSSOP16
96 Units per Rail
MC14053BDTEL
TSSOP16
2000 Units / Tape & Reel
MC14053BDTR2
TSSOP16
2500 Units / Tape & Reel
MC14053BF
SOEIAJ16
See Note 7.
MC14053BFEL
SOEIAJ16
See Note 7.
7. For ordering information on the EIAJ version of the SOIC
packages, please contact your local ON Semiconductor rep-
resentative.
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MC14051B/D
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