Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 3
1
Publication Order Number:
MC14076B/D
MC14076B
4-Bit D-Type Register
with Three-State Outputs
The MC14076B 4Bit Register consists of four Dtype flipflops
operating synchronously from a common clock. OR gated
outputdisable inputs force the outputs into a highimpedance state
for use in bus organized systems. OR gated datadisable inputs cause
the Q outputs to be fed back to the D inputs of the flipflops. Thus they
are inhibited from changing state while the clocking process remains
undisturbed. An asynchronous master root is provided to clear all four
flipflops simultaneously independent of the clock or disable inputs.
ThreeState Outputs with Gated Control Lines
Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing
Asynchronous Master Reset
Four Bus Buffer Registers
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 1.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
10
mA
P
D
Power Dissipation,
per Package (Note 2.)
500
mW
T
A
Ambient Temperature Range
55 to +125
C
T
stg
Storage Temperature Range
65 to +150
C
T
L
Lead Temperature
(8Second Soldering)
260
C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
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A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14076BCP
PDIP16
2000/Box
MC14076BD
SOIC16
2400/Box
MC14076BDR2
SOIC16
2500/Tape & Reel
MARKING
DIAGRAMS
1
16
PDIP16
P SUFFIX
CASE 648
MC14076BCP
AWLYYWW
SOIC16
D SUFFIX
CASE 751B
1
16
14076B
AWLYWW
MC14076B
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3
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
55
_
C
25
_
C
125
_
C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(3.)
Max
Min
Max
Unit
Output Voltage
"0" Level
V
in
= V
DD
or 0
V
OL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
"1" Level
V
in
= 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
--
--
--
1.5
3.0
4.0
--
--
--
2.25
4.50
6.75
1.5
3.0
4.0
--
--
--
1.5
3.0
4.0
Vdc
"1" Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
--
--
--
3.5
7.0
11
2.75
5.50
8.25
--
--
--
3.5
7.0
11
--
--
--
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc)
Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
--
--
--
--
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
--
--
--
--
1.7
0.36
0.9
2.4
--
--
--
--
mAdc
(V
OL
= 0.4 Vdc)
Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
--
--
--
0.51
1.3
3.4
0.88
2.25
8.8
--
--
--
0.36
0.9
2.4
--
--
--
mAdc
Input Current
I
in
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
(V
in
= 0)
C
in
--
--
--
--
5.0
7.5
--
--
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
--
--
--
5.0
10
20
--
--
--
0.005
0.010
0.015
5.0
10
20
--
--
--
150
300
600
Adc
Total Supply Current
(4.) (5.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
I
T
= (0.75
A/kHz) f + I
DD
I
T
= (1.50
A/kHz) f + I
DD
I
T
= (2.25
A/kHz) f + I
DD
Adc
ThreeState Leakage Current
I
TL
15
--
0.1
--
0.0001
0.1
--
3.0
Adc
3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
4. The formulas given are for the typical characteristics only at 25
_
C.
5. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
50) Vfk
where: I
T
is in
A (per package), C
L
in pF, V = (V
DD
V
SS
) in volts, f in kHz is input frequency, and k = 0.002.
MC14076B
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4
SWITCHING CHARACTERISTICS
(6.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Symbol
V
DD
Vdc
Min
Typ
(7.)
Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
, t
THL
5.0
10
15
--
--
--
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 215 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 92 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 65 ns
t
PLH
, t
PHL
5.0
10
15
--
--
--
300
125
90
600
250
180
ns
Reset to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 215 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 92 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 65 ns
5.0
10
15
--
--
--
300
125
90
600
250
180
3State Propagation Delay, Output "1" or "0"
to High Impedance
t
PHZ
, t
PLZ
5.0
10
15
--
--
--
150
60
45
300
120
90
ns
3State Propagation Delay, High Impedance
to "1" or "0" Level
t
PZH
, t
PZL
5.0
10
15
--
--
--
200
80
60
400
160
120
ns
Clock Pulse Width
t
WH
5.0
10
15
260
110
80
130
55
40
--
--
--
ns
Reset Pulse Width
t
WH
5.0
10
15
370
150
110
185
75
55
--
--
--
ns
Data Setup Time
t
su
5.0
10
15
30
10
4
15
5
2
--
--
--
ns
Data Hold Time
t
h
5.0
10
15
130
60
50
65
30
25
--
--
--
ns
Data Disable Setup Time
t
su
5.0
10
15
220
80
50
110
40
25
--
--
--
ns
Clock Pulse Rise and Fall Time
t
TLH
, t
THL
5.0
10
15
--
--
--
--
--
--
15
5
4
s
Clock Pulse Frequency
f
cl
5.0
10
15
--
--
--
3.6
9.0
12
1.8
4.5
6.0
MHz
6. The formulas given are for the typical characteristics only at 25
_
C.
7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
MC14076B
http://onsemi.com
5
Figure 1. Timing Diagram
INPUT RISE AND FALL 20 ns
D
INPUT
INFORMATION
V
DD
V
SS
V
SS
V
OH
V
OL
V
DD
Q
OUTPUT
90%
50%
10%
t
su
t
h
t
su
t
h
20 ns
90%
10%
50%
90%
10%
t
TLH
t
PHL
t
THL
50%
t
WH
t
WL
f
cl
RESET = 0
DATA DISABLE A AND B = 0
OUTPUT DISABLE A AND B = 0
Figure 2. ThreeState Propagation Delay
Waveshape and Circuit
MC14076B
OTHER
INPUTS
OUTPUT
DISABLE
A OR B
ANY Q
OUTPUT
R
L
= 1 k
C
L
V
DD
FOR t
PLZ
AND t
PZL
V
SS
FOR t
PHZ
AND t
PZH
OUTPUT
DISABLE
A OR B
ANY Q
OUTPUT
ANY Q
OUTPUT
20 ns
20 ns
V
DD
V
SS
V
OH
90%
50%
50%
10%
t
PLZ
t
PZL
90%
t
PZH
t
PHZ
90%
10%
10%
2.5 V @ V
DD
= 5 V,
10 V, AND 15 V
2 V @ V
DD
= 5 V
6 V @ V
DD
= 10 V
10 V @ V
DD
= 15 V
V
OL
OUTPUTS
CONNECTED
OUTPUTS
DISCONNECTED
OUTPUTS
CONNECTED
t
PLH
EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM
OUTPUT DISABLE A
OUTPUT DISABLE B
D0
1
2
14
DATA DISABLE A
DATA DISABLE B
9
10
D1 13
CLOCK
7
D2 12
D3
11
RESET 15
6
Q3
5
Q2
4
Q1
3
Q0
D
Q
R
C
Q
D
Q
R
C
Q
D
Q
R
C
Q
D
Q
R
C
Q
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