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Semiconductor Components Industries, LLC, 2004
April, 2004 - Rev. 8
1
Publication Order Number:
MC34071/D
MC34071,2,4,A
MC33071,2,4,A
Single Supply 3.0 V to 44 V
Operational Amplifiers
Quality bipolar fabrication with innovative design concepts are
employed for the MC33071/72/74, MC34071/72/74 series of
monolithic operational amplifiers. This series of operational
amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/
ms slew rate
and fast settling time without the use of JFET device technology.
Although this series can be operated from split supplies, it is
particularly suited for single supply operation, since the common
mode input voltage range includes ground potential (V
EE
). With a
Darlington input stage, this series exhibits high input resistance, low
input offset voltage and high gain. The all NPN output stage,
characterized by no deadband crossover distortion and large output
voltage swing, provides high capacitance drive capability, excellent
phase and gain margins, low open loop high frequency output
impedance and symmetrical source/sink AC frequency response.
The MC33071/72/74, MC34071/72/74 series of devices are
available in standard or prime performance (A Suffix) grades and are
specified over the commercial, industrial/vehicular or military
temperature ranges. The complete series of single, dual and quad
operational amplifiers are available in plastic DIP, SOIC and TSSOP
surface mount packages.
Features
Wide Bandwidth: 4.5 MHz
High Slew Rate: 13 V/
ms
Fast Settling Time: 1.1
ms to 0.1%
Wide Single Supply Operation: 3.0 V to 44 V
Wide Input Common Mode Voltage Range: Includes Ground (V
EE)
Low Input Offset Voltage: 3.0 mV Maximum (A Suffix)
Large Output Voltage Swing: -14.7 V to +14 V (with
15 V
Supplies)
Large Capacitance Drive Capability: 0 pF to 10,000 pF
Low Total Harmonic Distortion: 0.02%
Excellent Phase Margin: 60
Excellent Gain Margin: 12 dB
Output Short Circuit Protection
ESD Diodes/Clamps Provide Input Protection for Dual and Quad
Pb-Free Packages are Available
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See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
ORDERING INFORMATION
PDIP-8
P SUFFIX
CASE 626
1
8
SOIC-8
D SUFFIX
CASE 751
1
8
PDIP-14
P SUFFIX
CASE 646
1
14
SOIC-14
D SUFFIX
CASE 751A
1
14
TSSOP-14
DTB SUFFIX
CASE 948G
1
14
See general marking information in the device marking
section on page 18 of this data sheet.
DEVICE MARKING INFORMATION
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MC34071,2,4,A MC33071,2,4,A
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2
CASE 626/CASE 751
PIN CONNECTIONS
(Single, Top View)
(Dual, Top View)
Offset Null
V
EE
NC
V
CC
Output
Offset Null
Inputs
V
EE
Inputs 1
Inputs 2
Output 2
Output 1
V
CC
-
1
2
3
4
8
7
6
5
-
-
+
+
1
2
3
4
8
7
6
5
+
Inputs 1
Output 1
V
CC
Inputs 2
Output 2
Output 4
Inputs 4
V
EE
Inputs 3
Output 3
(Quad, Top View)
4
2
3
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
-
+
-
+
+
-
+
-
CASE 646/CASE 751A/CASE 948G
Offset Null
(MC33071, MC34071 only)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q17
Q18
D2
C2
D3
R6
R7
R8
R5
Q15
Q16
Q14
Q13
Q11
Q10
R2
C1
R1
Q9
Q8
Q12
D1
R3
R4
Inputs
V
CC
Output
Current
Limit
V
EE
/GND
Base
Current
Cancellation
-
+
Q19
Bias
Figure 1. Representative Schematic Diagram
(Each Amplifier)
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage (from V
EE
to V
CC
)
V
S
+44
V
Input Differential Voltage Range
V
IDR
(Note 1)
V
Input Voltage Range
V
IR
(Note 1)
V
Output Short Circuit Duration (Note 2)
t
SC
Indefinite
Sec
Operating Junction Temperature
T
J
+150
C
Storage Temperature Range
T
stg
-60 to +150
C
1. Either or both input voltages should not exceed the magnitude of V
CC
or V
EE
.
2. Power dissipation must be considered to ensure maximum junction temperature (T
J
) is not exceeded (see Figure 2).
MC34071,2,4,A MC33071,2,4,A
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3
ELECTRICAL CHARACTERISTICS
(V
CC
= +15 V, V
EE
= -15 V, R
L
= connected to ground, unless otherwise noted. See Note 3 for
T
A
= T
low
to T
high
)
A Suffix
Non-Suffix
Characteristics
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Input Offset Voltage (R
S
= 100
W
, V
CM
= 0 V, V
O
= 0 V)
V
CC
= +15 V, V
EE
= -15 V, T
A
= +25
C
V
CC
= +5.0 V, V
EE
= 0 V, T
A
= +25
C
V
CC
= +15 V, V
EE
= -15 V, T
A
= T
low
to T
high
V
IO
-
-
-
0.5
0.5
-
3.0
3.0
5.0
-
-
-
1.0
1.5
-
5.0
5.0
7.0
mV
Average Temperature Coefficient of Input Offset
Voltage
R
S
= 10
W
, V
CM
= 0 V, V
O
= 0 V,
T
A
= T
low
to T
high
D
V
IO
/
D
T
-
10
-
-
10
-
m
V/
C
Input Bias Current (V
CM
= 0 V, V
O
= 0 V)
T
A
= +25
C
T
A
= T
low
to T
high
I
IB
-
-
100
-
500
700
-
-
100
-
500
700
nA
Input Offset Current (V
CM
= 0 V, V
O
= 0V)
T
A
= +25
C
T
A
= T
low
to T
high
I
IO
-
-
6.0
-
50
300
-
-
6.0
-
75
300
nA
Input Common Mode Voltage Range
T
A
= +25
C
T
A
= T
low
to T
high
V
ICR
V
EE
to (V
CC
-1.8)
V
EE
to (V
CC
-2.2)
V
EE
to (V
CC
-1.8)
V
EE
to (V
CC
-2.2)
V
Large Signal Voltage Gain (V
O
=
10 V, R
L
= 2.0 k
W
)
T
A
= +25
C
T
A
= T
low
to T
high
A
VOL
50
25
100
-
-
-
25
20
100
-
-
-
V/mV
Output Voltage Swing (V
ID
=
1.0 V)
V
CC
= +5.0 V, V
EE
= 0 V, R
L
= 2.0 k
W
, T
A
= +25
C
V
CC
= +15 V, V
EE
= -15 V, R
L
= 10 k
W
, T
A
= +25
C
V
CC
= +15 V, V
EE
= -15 V, R
L
= 2.0 k
W
,
T
A
= T
low
to T
high
V
OH
3.7
13.6
13.4
4.0
14
-
-
-
-
3.7
13.6
13.4
4.0
14
-
-
-
-
V
V
CC
= +5.0 V, V
EE
= 0 V, R
L
= 2.0 k
W
, T
A
= +25
C
V
CC
= +15 V
,
V
EE
= -15 V, R
L
= 10 k
W
, T
A
= +25
C
V
CC
= +15 V, V
EE
= -15 V, R
L
= 2.0 k
W
,
T
A
= T
low
to T
high
V
OL
-
-
-
0.1
-14.7
-
0.3
-14.3
-13.5
-
-
-
0.1
-14.7
-
0.3
-14.3
-13.5
V
Output Short Circuit Current (V
ID
= 1.0 V, V
O
= 0 V,
T
A
= 25
C)
Source
Sink
I
SC
10
20
30
30
-
-
10
20
30
30
-
-
mA
Common Mode Rejection
R
S
10 k
W
, V
CM
= V
ICR
, T
A
= 25
C
CMR
80
97
-
70
97
-
dB
Power Supply Rejection (R
S
= 100
W
)
V
CC
/V
EE
= +16.5 V/-16.5 V to +13.5 V/-13.5 V,
T
A
= 25
C
PSR
80
97
-
70
97
-
dB
Power Supply Current (Per Amplifier, No Load)
V
CC
= +5.0 V, V
EE
= 0 V, V
O
= +2.5 V, T
A
= +25
C
V
CC
= +15 V, V
EE
= -15 V, V
O
= 0 V, T
A
= +25
C
V
CC
= +15 V, V
EE
= -15 V, V
O
= 0 V,
T
A
= T
low
to T
high
I
D
-
-
-
1.6
1.9
-
2.0
2.5
2.8
-
-
-
1.6
1.9
-
2.0
2.5
2.8
mA
3. T
low
= -40
C for MC33071, 2, 4, /A
T
high
= +85
C for MC33071, 2, 4, /A
= 0
C for MC34071, 2, 4, /A
= +70
C for MC34071, 2, 4, /A
= -40
C for MC34072, 4/V
= +125
C for MC34072, 4/V
MC34071,2,4,A MC33071,2,4,A
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4
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +15 V, V
EE
= -15 V, R
L
= connected to ground. T
A
= +25
C, unless otherwise noted.)
A Suffix
Non-Suffix
Characteristics
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Slew Rate (V
in
= -10 V to +10 V, R
L
= 2.0 k
W
, C
L
= 500 pF)
A
V
= +1.0
A
V
= -1.0
SR
8.0
-
10
13
-
-
8.0
-
10
13
-
-
V/
m
s
Setting Time (10 V Step, A
V
= -1.0)
To 0.1% (+1/2 LSB of 9-Bits)
To 0.01% (+1/2 LSB of 12-Bits)
t
s
-
-
1.1
2.2
-
-
-
-
1.1
2.2
-
-
m
s
Gain Bandwidth Product (f = 100 kHz)
GBW
3.5
4.5
-
3.5
4.5
-
MHz
Power Bandwidth
A
V
= +1.0, R
L
= 2.0 k
W
, V
O
= 20 V
pp
, THD = 5.0%
BW
-
160
-
-
160
-
kHz
Phase margin
R
L
= 2.0 k
W
R
L
= 2.0 k
W
, C
L
= 300 pF
f
m
-
-
60
40
-
-
-
-
60
40
-
-
Deg
Gain Margin
R
L
= 2.0 k
W
R
L
= 2.0 k
W
, C
L
= 300 pF
A
m
-
-
12
4.0
-
-
-
-
12
4.0
-
-
dB
Equivalent Input Noise Voltage
R
S
= 100
W
, f = 1.0 kHz
e
n
-
32
-
-
32
-
nV/ Hz
Equivalent Input Noise Current
f = 1.0 kHz
i
n
-
0.22
-
-
0.22
-
pA/ Hz
Differential Input Resistance
V
CM
= 0 V
R
in
-
150
-
-
150
-
M
W
Differential Input Capacitance
V
CM
= 0 V
C
in
-
2.5
-
-
2.5
-
pF
Total Harmonic Distortion
A
V
= +10, R
L
= 2.0 k
W
, 2.0 V
pp
V
O
20 V
pp
, f = 10 kHz
THD
-
0.02
-
-
0.02
-
%
Channel Separation (f = 10 kHz)
-
-
120
-
-
120
-
dB
Open Loop Output Impedance (f = 1.0 MHz)
|Z
O
|
-
30
-
-
30
-
W
Figure 2. Power Supply Configurations
Figure 3. Offset Null Circuit
Single Supply
Split Supplies
1
2
3
4
V
CC
V
EE
V
CC
V
CC
V
EE
V
EE
1
2
3
4
3.0 V to 44 V
V
CC
+|V
EE
|
44 V
Offset nulling range is approximately
80 mV with a 10 k
potentiometer (MC33071, MC34071 only).
V
CC
V
EE
1
2
3
4
5
6
7
10 k
+
-
MC34071,2,4,A MC33071,2,4,A
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5
R
L
Connected
to Ground T
A
= 25
C
R
L
= 10 k
R
L
= 2.0 k
V
O
, OUTPUT
VOL
T
AGE SWING (V
pp
)
Figure 4. Maximum Power Dissipation versus
Temperature for Package Types
Figure 5. Input Offset Voltage versus
Temperature for Representative Units
Figure 6. Input Common Mode Voltage
Range versus Temperature
Figure 7. Normalized Input Bias Current
versus Temperature
Figure 8. Normalized Input Bias Current versus
Input Common Mode Voltage
Figure 9. Split Supply Output Voltage
Swing versus Supply Voltage
T
A
, AMBIENT TEMPERATURE (
C)
D
P, MAXIMUM POWER DISSIP
A
TION (mW)
-55 -40 -20
0
20
40
60
80
100 120 140 160
8 & 14 Pin Plastic Pkg
SOIC-14 Pkg
SOIC-8 Pkg
T
A
, AMBIENT TEMPERATURE (
C)
IO
V, INPUT
OFFSET
VOL
T
AGE (mV)
-55
-25
0
25
50
75
100
125
V
CC
= +15 V
V
EE
= -15 V
V
CM
= 0
T
A
, AMBIENT TEMPERATURE (
C)
ICR
V, INPUT
COMMON MODE VOL
T
AGE RANGE (V)
-55
-25
0
25
50
75
100
125
V
CC
V
CC
/V
EE
= +1.5 V/ -1.5 V to +22 V/ -22 V
V
EE
T
A
, AMBIENT TEMPERATURE (
C)
IB
I, INPUT
BIAS CURRENT
(NORMALIZED)
-55
-25
0
25
50
75
100
125
V
CC
= +15 V
V
EE
= -15 V
V
CM
= 0
V
IC
, INPUT COMMON MODE VOLTAGE (V)
-12
-8.0
-4.0
0
4.0
8.0
12
V
CC
= +15 V
V
EE
= -15 V
T
A
= 25
C
V
CC
, |V
EE
|, SUPPLY VOLTAGE (V)
0
5.0
10
15
20
25
V
IB
I, INPUT
BIAS CURRENT
(NORMALIZED)
2400
2000
1600
1200
800
400
0
4.0
2.0
0
-2.0
-4.0
V
CC
V
CC
-0.8
V
CC
-1.6
V
CC
-2.4
V
EE
+0.01
V
EE
1.3
1.2
1.1
1.0
0.9
0.8
0.7
1.4
1.2
1.0
0.8
0.6
50
40
30
20
10
0
MC34071,2,4,A MC33071,2,4,A
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6
V
CC
V
CC
= +15 V
R
L
to V
CC
T
A
= 25
C
GND
V
CC
V
CC
= +15 V
R
L
= GND
T
A
= 25
C
GND
V
O
, OUTPUT
VOL
T
AGE SWING (V
pp
)
Figure 10. Single Supply Output Saturation
versus Load Resistance to V
CC
60
Figure 11. Split Supply Output Saturation
versus Load Current
Figure 12. Single Supply Output Saturation
versus Load Resistance to Ground
Figure 13. Output Short Circuit Current
versus Temperature
Figure 14. Output Impedance
versus Frequency
Figure 15. Output Voltage Swing
versus Frequency
0
5.0
10
15
20
I
L,
LOAD CURRENT (
mA)
V
CC
V
EE
Sink
V
CC
/V
EE
= +5.0 V/ -5.0 V to +22 V/ -22 V
T
A
= 25
C
Source
R
L
, LOAD RESISTANCE TO GROUND (
W)
100
1.0 k
10 k
100 k
sat
V , OUTPUT
SA
TURA
TION VOL
T
AGE (V)
R
L
, LOAD RESISTANCE TO V
CC
(
W)
100
1.0 k
10 k
100 k
T
A
, AMBIENT TEMPERATURE (
C)
SCI, OUTPUT
CURRENT
(mA)
-55
-25
0
25
50
75
100
125
V
CC
= +15 V
V
EE
= -15 V
R
L
0.1
W
DV
in
= 1.0 V
Sink
Source
f, FREQUENCY (Hz)
O
Z, OUTPUT
IMPEDANCE ()
1.0 k
10 k
100
1.0 M
10 M
A
V
= 1000
A
V
= 100
A
V
= 10
A
V
= 1.0
V
CC
= +15 V
V
EE
= -15 V
V
CM
= 0
V
O
= 0
DI
O
=
0.5 mA
T
A
= 25
C
f, FREQUENCY (Hz)
3.0 k
10 k
30 k
100 k
300 k
1.0 M
3.0 M
V
CC
= +15 V
V
EE
= -15 V
A
V
= +1.0
R
L
= 2.0 k
THD
1.0%
T
A
= 25
C
sat
V , OUTPUT
SA
TURA
TION VOL
T
AGE (V)
sat
V , OUTPUT
SA
TURA
TION VOL
T
AGE (V)
V
CC
V
CC
-1.0
V
CC
-2.0
V
EE
+2.0
V
EE
+1.0
V
EE
V
CC
-2.0
V
CC
-4.0
V
CC
0.2
0.1
0
0
-0.4
-0.8
2.0
1.0
50
40
30
20
10
0
50
40
30
20
10
0
28
24
20
16
12
8.0
4.0
0
MC34071,2,4,A MC33071,2,4,A
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7
1. Phase R
L
= 2.0 k
2. Phase R
L
= 2.0 k, C
L
= 300 pF
3. Gain R
L
= 2.0 k
4. Gain R
L
= 2.0 k, C
L
= 300 pF
V
CC
= +15 V
V
EE
= 15 V
V
O
= 0 V
T
A
= 25
C
Phase
Margin = 60
Gain
Margin = 12 dB
3
4
1
2
Gain
V
CC
= +15 V
V
EE
= -15 V
V
O
= 0 V
R
L
= 2.0 k
T
A
= 25
C
Phase
Phase
Margin
= 60
Figure 16. Total Harmonic Distortion
versus Frequency
Figure 17. Total Harmonic Distortion
versus Output Voltage Swing
Figure 18. Open Loop Voltage Gain
versus Temperature
Figure 19. Open Loop Voltage Gain and
Phase versus Frequency
Figure 20. Open Loop Voltage Gain and
Phase versus Frequency
Figure 21. Normalized Gain Bandwidth
Product versus Temperature
f, FREQUENCY (Hz)
10
100
1.0 k
10 k
100 k
A
V
= 1000
A
V
= 100
A
V
= 10
A
V
= 1.0
V
CC
= +15 V
V
EE
= -15 V
V
O
= 2.0 V
pp
R
L
= 2.0 k
T
A
= 25
C
V
O
, OUTPUT VOLTAGE SWING (V
pp
)
THD,
T
O
T
A
L
HARMONIC DIST
OR
TION (%)
0
4.0
8.0
12
16
20
V
CC
= +15 V
V
EE
= -15 V
R
L
= 2.0 k
T
A
= 25
C
A
V
= 1000
A
V
= 100
A
V
= 10
A
V
= 1.0
T
A
, AMBIENT TEMPERATURE (
C)
-55
-25
0
25
50
75
100
125
V
CC
= +15 V
V
EE
= -15 V
V
O
= -10 V to +10 V
R
L
= 10 k
f
10Hz
f, FREQUENCY (Hz)
1.0
10
100
1.0 k
10 k
100 k
1.0 M
10 M
100 M
, EXCESS PHASE (DEGREES)
, EXCESS PHASE (DEGREES)
f, FREQUENCY (MHz)
1.0
2.0
3.0
5.0
7.0
10
20
30
T
A
, AMBIENT TEMPERATURE (
C)
GBW
, GAIN BANDWIDTH PRODUCT
(NORMALIED)
-55
-25
0
25
50
75
100
125
V
CC
= +15 V
V
EE
= -15 V
R
L
= 2.0 k
VOL
A, OPEN LOOP
VOL
T
AGE GAIN (dB)
0.4
0.3
0.2
0.1
0
4.0
3.0
2.0
1.0
0
116
112
108
104
100
96
100
80
60
40
20
0
20
10
0
-10
-20
-30
-40
1.15
1.1
1.05
1.0
0.95
0.9
0.85
0
45
90
135
180
100
120
140
160
180
THD,
T
O
T
A
L
HARMONIC DIST
OR
TION (%)
VOL
A, OPEN LOOP
VOL
T
AGE GAIN (dB)
VOL
A, OPEN LOOP
VOL
T
AGE GAIN (dB)
MC34071,2,4,A MC33071,2,4,A
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8
V
CC
= +15 V
V
EE
= -15 V
A
V
= +1.0
R
L
= 2.0 k to
R
V
O
= -10 V to +10 V
T
A
= 25
C
Figure 22. Percent Overshoot versus
Load Capacitance
Figure 23. Phase Margin versus
Load Capacitance
Figure 24. Gain Margin versus Load Capacitance
Figure 25. Phase Margin versus Temperature
Figure 26. Gain Margin versus Temperature
Figure 27. Phase Margin and Gain Margin
versus Differential Source Resistance
PERCENT
OVERSHOOT
C
L
, LOAD CAPACITANCE (pF)
10
100
1.0 k
10 k
V
CC
= +15 V
V
EE
= -15 V
R
L
= 2.0 k
V
O
= -10 V to +10 V
T
A
= 25
C
C
L
, LOAD CAPACITANCE (pF)
, PHASE MARGIN (DEGREES)
m
10
100
1.0 k
10 k
V
CC
= +15 V
V
EE
= -15 V
A
V
= +1.0
R
L
= 2.0 k to
V
O
= -10 V to +10 V
T
A
= 25
C
C
L
, LOAD CAPACITANCE (pF)
m
A, GAIN MARGIN (dB)
10
100
1.0 k
10 k
, PHASE MARGIN (DEGREES)
m
T
A
, AMBIENT TEMPERATURE (
C)
-55
-25
0
25
50
75
100
125
V
CC
= +15 V
V
EE
= -15 V
A
V
= +1.0
R
L
= 2.0 k to
V
O
= -10 V to +10 V
C
L
= 10 pF
C
L
= 100 pF
C
L
= 1,000 pF
C
L
= 10,000 pF
T
A
, AMBIENT TEMPERATURE (
C)
-55
-25
0
25
50
75
100
125
V
CC
= +15 V
V
EE
= -15 V
A
V
= +1.0
R
L
= 2.0 k to
V
O
= -10 V to +10 V
C
L
= 10 pF
C
L
= 1,000 pF
m
A, GAIN MARGIN (dB)
C
L
= 100 pF
C
L
= 10,000 pF
Phase
m
A, GAIN MARGIN (dB)
R
T
, DIFFERENTIAL SOURCE RESISTANCE (
W)
1.0
100
1.0 k
10 k
10
100 k
R
1
R
2
V
O
+
-
V
CC
= +15 V
V
EE
= -15 V
R
T
= R
1
+ R
2
A
V
= +100
V
O
= 0 V
T
A
= 25
C
Gain
, PHASE MARGIN (DEGREES)
m
100
80
60
40
20
0
70
60
50
40
30
20
10
0
14
12
10
8.0
6.0
2.0
0
4.0
80
60
40
20
0
16
12
8.0
4.0
0
12
10
8.0
6.0
4.0
2.0
0
60
50
40
30
20
10
0
70
MC34071,2,4,A MC33071,2,4,A
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Figure 28. Normalized Slew Rate
versus Temperature
Figure 29. Output Settling Time
Figure 30. Small Signal Transient Response
Figure 31. Large Signal Transient Response
Figure 32. Common Mode Rejection
versus Frequency
Figure 33. Power Supply Rejection
versus Frequency
T
A
, AMBIENT TEMPERATURE (
C)
SR, SLEW RA
TE (NORMALIZED)
-55
-25
0
25
50
75
100
125
V
CC
= +15 V
V
EE
= -15 V
A
V
= +1.0
R
L
= 2.0 k
C
L
= 500 pF
t
s
, SETTLING TIME (
ms)
O
V, OUTPUT
VOL
T
AGE SWING FROM 0 V (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
CC
= +15 V
V
EE
= -15 V
A
V
= -1.0
T
A
= 25
C
10 mV
1.0 mV
1.0 mV
Compensated
Uncompensated
10 mV
1.0 mV
1.0 mV
50 mV/DIV
2.0
ms/DIV
V
CC
= +15 V
V
EE
= -15 V
A
V
= +1.0
R
L
= 2.0 k
C
L
= 300 pF
T
A
= 25
C
5.0 V/DIV
1.0
ms/DIV
f, FREQUENCY (Hz)
CMR, COMMON MODE REJECTION (dB)
0.1
1.0
10
100
1.0 k
10 k
100 k
1.0 M
10 M
T
A
= 25
C
T
A
= 125
C
T
A
= -55
C
V
CC
= +15 V
V
EE
= -15 V
V
CM
= 0 V
DV
CM
=
1.5 V
f, FREQUENCY (Hz)
PSR, POWER SUPPL
Y
REJECTION (dB)
0.1
1.0
10
100
1.0 k
10 k
100 k
1.0 M 10 M
V
CC
= +15 V
V
EE
= -15 V
T
A
= 25
C
(
DV
CC
= +1.5 V)
(
DV
EE
= +1.5 V)
+PSR
-PSR
V
CC
= +15 V
V
EE
= -15 V
A
V
= +1.0
R
L
= 2.0 k
C
L
= 300 pF
T
A
= 25
C
1.15
1.1
1.05
1.0
0.95
0.9
0.85
10
5.0
0
-5.0
-10
0
0
100
80
60
40
20
0
100
80
60
40
20
0
DV
CM
DV
O
A
DM
CMR = 20 Log
DV
CM
DV
O
x A
DM
+
-
DV
O
A
DM
+
-
DV
CC
DV
EE
DV
O
/A
DM
DV
CC
+PSR = 20 Log
DV
O
/A
DM
DV
EE
-PSR = 20 Log
MC34071,2,4,A MC33071,2,4,A
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Figure 34. Supply Current versus
Supply Voltage
Figure 35. Power Supply Rejection
versus Temperature
Figure 36. Channel Separation versus Frequency
Figure 37. Input Noise versus Frequency
V
CC
, |V
EE
|, SUPPLY VOLTAGE (V)
CCI , SUPPL
Y
CURRENT
(mA)
0
5.0
10
15
20
25
T
A
= 25
C
T
A
= 125
C
T
A
= -55
C
T
A
, AMBIENT TEMPERATURE (
C)
PSR, POWER SUPPL
Y
REJECTION (dB)
-55
-25
0
25
50
75
100
125
V
CC
= +15 V
V
EE
= -15 V
(
DV
CC
= +1.5 V)
(
DV
EE
= +1.5 V)
+PSR
-PSR
f, FREQUENCY (kHz)
CHANNEL
SEP
ARA
TION (dB)
10
20
30
50
70
100
200
300
V
CC
= +15 V
V
EE
= -15 V
T
A
= 25
C
f, FREQUENCY (kHz)
n
e, INPUT
NOICE VOL
T
AGE (
i, INPUT
NOISE CURRENT
(pA
)
10
100
1.0 k
10 k
100 k
nV
Hz)
Hz
n
Voltage
Current
9.0
8.0
7.0
6.0
5.0
4.0
105
95
85
75
65
120
100
80
60
40
20
0
70
60
50
40
30
20
10
0
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
DV
O
A
DM
+
-
DV
CC
DV
EE
DV
O
/A
DM
DV
CC
+PSR = 20 Log
DV
O
/A
DM
DV
EE
-PSR = 20 Log
V
CC
= +15 V
V
EE
= -15 V
V
CM
= 0
T
A
= 25
C
APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
MC34071 amplifier series are similar to op amp products
utilizing JFET input devices, these amplifiers offer other
additional distinct advantages as a result of the PNP
transistor differential input stage and an all NPN transistor
output stage.
Since the input common mode voltage range of this input
stage includes the V
EE
potential, single supply operation is
feasible to as low as 3.0 V with the common mode input
voltage at ground potential.
The input stage also allows differential input voltages up
to
44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between V
EE
and V
CC
supply voltages as shown by the
maximum rating table. In practice, although not
recommended, the input voltages can exceed the V
CC
voltage by approximately 3.0 V and decrease below the V
EE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
up to approximately 5.0 mA of current from V
EE
through
either inputs clamping diode without damage or latching,
although phase reversal may again occur.
If one or both inputs exceed the upper common mode
voltage limit, the amplifier output is readily predictable and
may be in a low or high state depending on the existing input
bias conditions.
Since the input capacitance associated with the small
geometry input device is substantially lower (2.5 pF) than
the typical JFET input gate capacitance (5.0 pF), better
frequency response for a given input source resistance can
be achieved using the MC34071 series of amplifiers. This
performance feature becomes evident, for example, in fast
settling D-to-A current to voltage conversion applications
where the feedback resistance can form an input pole with
the input capacitance of the op amp. This input pole creates
a 2nd order system with the single pole op amp and is
therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
MC34071,2,4,A MC33071,2,4,A
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11
values of feedback resistances (lower current DACs). This
input pole can be compensated for by creating a feedback
zero with a capacitance across the feedback resistance, if
necessary, to reduce overshoot. For 2.0 k
W of feedback
resistance, the MC34071 series can settle to within 1/2 LSB
of 8-bits in 1.0
ms, and within 1/2 LSB of 12-bits in 2.2 ms
for a 10 V step. In a inverting unity gain fast settling
configuration, the symmetrical slew rate is
13 V/
ms. In the
classic noninverting unity gain configuration, the output
positive slew rate is +10 V/
ms, and the corresponding
negative slew rate will exceed the positive slew rate as a
function of the fall time of the input waveform.
Since the bipolar input device matching characteristics
are superior to that of JFETs, a low untrimmed maximum
offset voltage of 3.0 mV prime and 5.0 mV downgrade can
be economically offered with high frequency performance
characteristics. This combination is ideal for low cost
precision, high speed quad op amp applications.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. A 10 k
W load resistance can swing within 1.0 V of the
positive rail (V
CC
), and within 0.3 V of the negative rail
(V
EE
), providing a 28.7 V
pp
swing from
15 V supplies.
This large output swing becomes most noticeable at lower
supply voltages.
The positive swing is limited by the saturation voltage of
the current source transistor Q
7
, and V
BE
of the NPN pull up
transistor Q
17
, and the voltage drop associated with the short
circuit resistance, R
7
. The negative swing is limited by the
saturation voltage of the pull-down transistor Q
16
, the
voltage drop I
L
R
6
, and the voltage drop associated with
resistance R
7
, where I
L
is the sink load current. For small
valued sink currents, the above voltage drops are negligible,
allowing the negative swing voltage to approach within
millivolts of V
EE
. For large valued sink currents (>5.0 mA),
diode D3 clamps the voltage across R
6
, thus limiting the
negative swing to the saturation voltage of Q
16
, plus the
forward diode drop of D3 (
V
EE
+1.0 V). Thus for a given
supply voltage, unprecedented peak-to-peak output voltage
swing is possible as indicated by the output swing
specifications.
If the load resistance is referenced to V
CC
instead of
ground for single supply applications, the maximum
possible output swing can be achieved for a given supply
voltage. For light load currents, the load resistance will pull
the output to V
CC
during the positive swing and the output
will pull the load resistance near ground during the negative
swing. The load resistance value should be much less than
that of the feedback resistance to maximize pull up
capability.
Because the PNP output emitter-follower transistor has
been eliminated, the MC34071 series offers a 20 mA
minimum current sink capability, typically to an output
voltage of (V
EE
+1.8 V). In single supply applications the
output can directly source or sink base current from a
common emitter NPN transistor for fast high current
switching applications.
In addition, the all NPN transistor output stage is
inherently fast, contributing to the bipolar amplifier's high
gain bandwidth product and fast settling capability. The
associated high frequency low output impedance (30
W typ
@ 1.0 MHz) allows capacitive drive capability from 0 pF to
10,000 pF without oscillation in the unity closed loop gain
configuration. The 60
phase margin and 12 dB gain margin
as well as the general gain and phase characteristics are
virtually independent of the source/sink output swing
conditions. This allows easier system phase compensation,
since output swing will not be a phase consideration. The
high frequency characteristics of the MC34071 series also
allow excellent high frequency active filter capability,
especially for low voltage single supply applications.
Although the single supply specifications is defined at
5.0 V, these amplifiers are functional to 3.0 V @ 25
C
although slight changes in parametrics such as bandwidth,
slew rate, and DC gain may occur.
If power to this integrated circuit is applied in reverse
polarity or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
Special static precautions are not necessary for these
bipolar amplifiers since there are no MOS transistors on the
die.
As with most high frequency amplifiers, proper lead
dress, component placement, and PC board layout should be
exercised for optimum frequency performance. For
example,
long unshielded input or output leads may result in
unwanted input-output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole for optimum frequency response, but also minimizes
extraneous "pick up" at this node. Supply decoupling with
adequate capacitance immediately adjacent to the supply pin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However, under
such conditions, it is important not to allow the device to
exceed the maximum junction temperature rating. Typically
for
15 V supplies, any one output can be shorted
continuously to ground without exceeding the maximum
temperature rating.
MC34071,2,4,A MC33071,2,4,A
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12
Figure 38. AC Coupled Noninverting Amplifier
Figure 39. AC Coupled Inverting Amplifier
(Typical Single Supply Applications V
CC
= 5.0 V)
Figure 40. DC Coupled Inverting Amplifier
Maximum Output Swing
Figure 41. Unity Gain Buffer TTL Driver
Figure 42. Active High-Q Notch Filter
Figure 43. Active Bandpass Filter
-
+
V
CC
5.1 M
20 k
C
in
V
in
1.0 M
MC34071
V
O
0
3.7 V
pp
R
L
10 k
A
V
= 101
100 k
1.0 k
BW (-3.0 dB) = 45 kHz
C
O
V
O
36.6 mV
pp
-
+
3.7 V
pp
0
V
CC
V
O
100 k
C
in
10 k
100 k
C
O
R
L
10 k
68 k
V
in
370 mV
pp
A
V
= 10 BW (-3.0 dB) = 450 kHz
+
-
4.75 V
pp
V
O
V
O
V
CC
R
L
100 k
91 k
5.1 k
1.0 M
A
V
= 10
V
in
2.63 V
5.1 k
BW (-3.0 dB) = 450 kHz
-
+
V
in
2.5 V
0
0 to 10,000 pF
Cable
TTL Gate
-
+
V
in
V
O
16 k
C
0.01
32 k
2.0 R
2.0 C
0.02
f
o
= 1.0 kHz
f
o
=
V
in
0.2 Vdc
1
4
pRC
2.0 C
0.02
16 k
R
R
-
+
V
in
V
O
V
CC
R3
2.2 k
C
0.047
R2
5.6 k
0.4 V
CC
R1
f
o
= 30 kHz
H
o
= 10
H
o
= 1.0
1.1 k
Given f
o
= Center Frequency
A
O
= Gain at Center Frequency
Choose Value f
o
, Q, A
o
, C
R3 =
R1 =
R2 =
Q
R3
R1 R3
2H
o
4Q
2
R1-R3
pf
o
C
For less than 10% error from operational amplifier
Q
o
f
o
GBW
< 0.1
where f
o
and GBW are expressed in Hz.
C
0.047
MC34071
MC34071
MC34071
MC34071
MC34071
MC54/74XX
Then:
GBW = 4.5 MHz Typ.
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com
13
Figure 44. Low Voltage Fast D/A Converter
Figure 45. High Speed Low Voltage Comparator
Figure 46. LED Driver
Figure 47. Transistor Driver
Figure 48. AC/DC Ground Current Monitor
Figure 49. Photovoltaic Cell Amplifier
5.0 k
10 k
Bit
Switches
C
F
R
F
V
O
V
CC
(R-2R) Ladder Network
Settling Time
1.0
ms (8-Bits, 1/2 LSB)
-
+
5.0 k
5.0 k
10 k
10 k
-
+
V
O
V
O
V
in
1.0 V
2.0 k
R
L
2.0 V
4.0 V
0.1
t
25 V/
ms
0.2
ms
Delay
Delay
1.0
ms
V
in
t
13 V/
ms
-
+
V
CC
V
ref
ON"
V
in
< V
ref
ON"
V
in
> V
ref
V
in
-
+
V
CC
V
CC
R
L
R
L
(A) PNP
(B) NPN
-
+
-
+
V
O
I
Load
R1
R2
R
S
Ground Current
Sense Resistor
V
O
= I
Load
R
S
BW ( -3.0 dB) = GBW
For V
O
> 0.1V
R1
R2
R1+R2
R2
-
+
V
O
MC34071
I
Cell
V
Cell
= 0 V
V
O
= I
Cell
R
F
V
O
> 0.1 V
R
F
1+
MC34071
MC34071
MC34071
MC34071
MC34071
MC34071
MC34071,2,4,A MC33071,2,4,A
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14
Figure 50. Low Input Voltage Comparator
with Hysteresis
Figure 51. High Compliance Voltage to
Sink Current Converter
Figure 52. High Input Impedance
Differential Amplifier
Figure 53. Bridge Current Amplifier
Figure 54. Low Voltage Peak Detector
Figure 55. High Frequency Pulse
Width Modulation
V
ref
R2
V
O
V
OH
V
OL
V
inL
V
inH
V
ref
Hysteresis
V
in
V
in
R1
MC34071
V
inL
=
(V
OL
-V
ref
)+V
ref
R1
R1+R2
V
inH
=
(V
OH
-V
ref
)+V
ref
V
H
=
(V
OH
-V
OL
)
+
-
R1
R1+R
R1
R1+R2
V
in
I
out
R
-
+
I
out
=
V
in
V
IO
R
1/2
MC34072
-
+
+
R1
R2
R3
R4
V
O
+V1
+V2
R2
R4
R3
R1
(Critical to CMRR)
V
O
= 1
V2-V1
For (V2
V1), V > 0
=
-
+
R4
R3
R4
R3
-
+
+V
ref
R
F
V
O
R
R
R
R =
DR
DR < < R
R
F
> > R
(V
O
0.1 V)
R
F
V
O
= V
ref
DR R
F
2R
2
-
+
V
in
V
in
R
L
V
P
10,000 pF
V
O
= V
in
(pk)
+
V
P
t
-
+
+
V
P
t
t
I
out
V
P
+
-
0
+
I
SC
Base Charge
Removal
I
B
V+
47 k
100 k
C
R
Pulse Width
Control Group
OSC
Comparator
High Current
Output
f
OSC
^
V
0.85
RC
-
100 k
I
B
MC34071
MC34071
MC34071
1/2
MC34072
1/2
MC34072
1/2
MC34072
MC34071,2,4,A MC33071,2,4,A
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15
Figure 56. Second Order Low-Pass Active Filter
Figure 57. Second Order High-Pass Active Filter
GENERAL ADDITIONAL APPLICATIONS INFORMATION V
S
=
15.0 V
Figure 58. Fast Settling Inverter
Figure 59. Basic Inverting Amplifier
Figure 60. Basic Noninverting Amplifier
Figure 61. Unity Gain Buffer (A
V
= +1.0)
-
+
R1
R3
560
510
C2
C1
0.44
0.02
R2
5.6 k
MC34071
f
o
= 1.0 kHz
H
o
= 10
Choose: f
o
, H
o
, C2
Then: C1 = 2C2 (H
o
+1)
R2 =
R3 =
R1 =
R2
H
o
H
o
+1
4
pf
o
C2
R2
+
-
C2
0.05
C1
1.0
R1
46.1 k
R2
1.1 k
f
o
= 100 Hz
H
o
= 20
Choose: f
o
, H
o
, C1
Then: R1 =
R2 =
C2 =
H
o
+0.5
pf
o
C1
2
pf
o
C1 (1/H
o
+2)
C
H
o
C1
1.0
+
-
C
F
*
V
O
= 10 V
Step
R
F
2.0 k
I
High Speed
DAC
*Optional Compensation
Uncompensated
Compensated
t
s
= 1.0
ms
to 1/2 LSB (8-Bits)
t
s
= 2.2
ms
to 1/2 LSB (12-Bits)
SR = 13 V/
ms
V
O
+
-
R1
R2
V
O
V
in
R
L
BW (-3.0 dB) = GBW
=
SR = 13 V/
ms
V
O
V
in
R2
R1
R1 +R2
R1
BW (-3.0 dB) = GBW
R1 +R2
R1
+
-
V
in
V
O
R2
R
L
R1
=
V
O
V
in
R2
R1
1 +
+
-
V
in
V
O
BW
p
= 200 kHz
V
O
= 20 V
pp
SR = 10 V/
ms
MC34071
MC34071
MC34071
MC34071
MC34071
2
2
2
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com
16
Figure 62. High Impedance Differential Amplifier
Figure 63. Dual Voltage Doubler
-
R
R
E
Example:
Let: R = R
E
= 12 k
Then: A
V
= 3.0
BW = 1.5 MHz
A
V
= 1 + 2
R
R
E
-
-
+
+
+
V
O
R
R
R
R
R
MC34074
-
+
+
100 k
10
+10
-10
220 pF
-V
O
+V
O
R
L
+V
O
-V
O
18.93
-18.78
10 k
18
-18
5.0 k
15.4
-15.4
R
L
100 k
100 k
R
L
+
+
-
+
+
+
10
10
10
-
MC34074
MC34074
MC34074
MC34074
MC34074
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com
17
ORDERING INFORMATION
Op Amp
Function
Device
Operating
Temperature Range
Package
Shipping
MC34071P
PDIP-8
50 Units / Rail
MC34071AP
PDIP-8
50 Units / Rail
Single
MC34071D
T = 0
to +70
C
SOIC-8
98 Units / Rail
Single
MC34071AD
T
A
= 0
to +70
C
SOIC-8
98 Units / Rail
MC34071DR2
SOIC-8
2500 Units / Tape & Reel
MC34071ADR2
SOIC-8
2500 Units / Tape & Reel
MC34072P
PDIP-8
50 Units / Rail
MC34072PG
PDIP-8
(Pb-Free)
50 Units / Rail
MC34072AP
PDIP-8
50 Units / Rail
MC34072D
SOIC-8
98 Units / Rail
MC34072DG
T = 0
to +70
C
SOIC-8
(Pb-Free)
98 Units / Rail
MC34072AD
T
A
= 0
to +70
C
SOIC-8
98 Units / Rail
MC34072DR2
SOIC-8
2500 Units / Tape & Reel
MC34072DR2G
SOIC-8
(Pb-Free)
2500 Units / Tape & Reel
MC34072ADR2
SOIC-8
2500 Units / Tape & Reel
Dual
MC34072ADR2G
SOIC-8
(Pb-Free)
2500 Units / Tape & Reel
MC33072P
PDIP-8
1000 Units / Rail
MC33072PG
PDIP-8
(Pb-Free)
1000 Units / Tube
MC33072AP
PDIP-8
50 Units / Rail
MC33072D
T
40
to +85
C
SOIC-8
98 Units / Rail
MC33072AD
T
A
= -40
to +85
C
SOIC-8
98 Units / Rail
MC33072DR2
SOIC-8
2500 Units / Tape & Reel
MC33072DR2G
SOIC-8
(Pb-Free)
2500 Units / Tape & Reel
MC33072ADR2
SOIC-8
2500 Units / Tape & Reel
MC34072VD
SOIC-8
98 Units / Rail
MC34072VDR2
T
A
= -40
to +125
C
SOIC-8
2500 Units / Tape & Reel
MC34072VP
A
0
o
5 C
PDIP-8
50 Units / Rail
MC34074P
PDIP-14
25 Units / Rail
MC34074AP
PDIP-14
25 Units / Rail
MC34074D
SOIC-14
55 Units / Rail
MC34074AD
T
A
= 0
to +70
C
SOIC-14
55 Units / Rail
MC34074DR2
T
A
= 0
to +70
C
SOIC-14
2500 Units / Tape & Reel
MC34074DR2G
SOIC-14
(Pb-Free)
2500 Units / Tape & Reel
Quad
MC34074ADR2
SOIC-14
2500 Units / Tape & Reel
Quad
MC33074P
PDIP-14
25 Units / Rail
MC33074AP
PDIP-14
25 Units / Rail
MC33074D, MC33074AD
SOIC-14
55 Units / Rail
MC33074DR2
SOIC-14
2500 Units / Tape & Reel
MC33074ADR2
T
A
= -40
to +85
C
SOIC-14
2500 Units / Tape & Reel
MC33074DTB
TSSOP-14
(Pb-Free)
96 Units / Rail
MC33074ADTB
TSSOP-14
(Pb-Free)
96 Units / Rail
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com
18
Op Amp
Function
Device
Operating
Temperature Range
Package
Shipping
MC33074DTBR2
T = 40
to +85
C
TSSOP-14
(Pb-Free)
2500 Units / Tape & Reel
MC33074ADTBR2
T
A
= -40
to +85
C
TSSOP-14
(Pb-Free)
2500 Units / Tape & Reel
Quad
MC34074VD
SOIC-14
55 Units / Rail
Quad
MC34074VDG
T
A
= -40
to +125
C
SOIC-14
(Pb-Free)
55 Units / Rail
MC34074VDR2
T
A
40 to +125 C
SOIC-14
2500 Units / Tape & Reel
MC34074VP
PDIP-14
25 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
AWL
MC3x071P
1
8
YYWW
AWL
MC3x071AP
1
8
YYWW
ALYW
3x071
1
8
ALYWA
3x071
1
8
x
= 3 or 4
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
AWL
MC3x072P
1
8
YYWW
PPDIP-8
P SUFFIX
CASE 626
AWL
MC3x072AP
1
8
YYWW
ALYW
3x072
1
8
ALYWA
3x072
1
8
SOIC-8
D SUFFIX
CASE 751
ALYWV
3x072
1
8
1
14
MC3x074P
AWLYYWW
PPDIP-14
P SUFFIX
CASE 646
1
14
MC3x074AP
AWLYYWW
1
14
MC3x074D
AWLYWW
1
14
MC3x074AD
AWLYWW
MC33
074
ALYW
1
14
TSSOP-14
DTB SUFFIX
CASE 948G
MC33
074A
ALYW
1
14
SOIC-14
D SUFFIX
CASE 751A
1
14
MC34074VD
AWLYWW
AWL
MC34072VP
1
8
YYWW
1
14
MC34074VP
AWLYYWW
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com
19
PACKAGE DIMENSIONS
PDIP-8
P SUFFIX
CASE 626-05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1
4
5
8
F
NOTE 2
-A-
-B-
-T-
SEATING
PLANE
H
J
G
D
K
N
C
L
M
M
A
M
0.13 (0.005)
B
M
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.40
10.16
0.370
0.400
B
6.10
6.60
0.240
0.260
C
3.94
4.45
0.155
0.175
D
0.38
0.51
0.015
0.020
F
1.02
1.78
0.040
0.070
G
2.54 BSC
0.100 BSC
H
0.76
1.27
0.030
0.050
J
0.20
0.30
0.008
0.012
K
2.92
3.43
0.115
0.135
L
7.62 BSC
0.300 BSC
M
---
10
---
10
N
0.76
1.01
0.030
0.040
_
_
MC34071,2,4,A MC33071,2,4,A
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20
PACKAGE DIMENSIONS
SOIC-8
D SUFFIX
CASE 751-07
ISSUE AB
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
SOLDERING FOOTPRINT*
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN
MAX
MIN
MAX
INCHES
4.80
5.00
0.189
0.197
MILLIMETERS
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.053
0.069
D
0.33
0.51
0.013
0.020
G
1.27 BSC
0.050 BSC
H
0.10
0.25
0.004
0.010
J
0.19
0.25
0.007
0.010
K
0.40
1.27
0.016
0.050
M
0
8
0
8
N
0.25
0.50
0.010
0.020
S
5.80
6.20
0.228
0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010)
Z
S
X
S
M
_
_
_
_
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com
21
PACKAGE DIMENSIONS
PDIP-14
P SUFFIX
CASE 646-06
ISSUE M
1
7
14
8
B
A
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.715
0.770
18.16
18.80
B
0.240
0.260
6.10
6.60
C
0.145
0.185
3.69
4.69
D
0.015
0.021
0.38
0.53
F
0.040
0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052
0.095
1.32
2.41
J
0.008
0.015
0.20
0.38
K
0.115
0.135
2.92
3.43
L
M
---
10 ---
10
N
0.015
0.039
0.38
1.01
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
H
G
D
K
C
SEATING
PLANE
N
-T-
14 PL
M
0.13 (0.005)
L
M
J
0.290
0.310
7.37
7.87
SOIC-14
D SUFFIX
CASE 751A-03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
-A-
-B-
G
P
7 PL
14
8
7
1
M
0.25 (0.010)
B
M
S
B
M
0.25 (0.010)
A
S
T
-T-
F
R
X 45
SEATING
PLANE
D
14 PL
K
C
J
M
_
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
8.55
8.75
0.337
0.344
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.228
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com
22
PACKAGE DIMENSIONS
S
U
0.15 (0.006) T
2X
L/2
S
U
M
0.10 (0.004)
V
S
T
L
-U-
SEATING
PLANE
0.10 (0.004)
-T-
SECTION N-N
DETAIL E
J J1
K
K1
DETAIL E
F
M
-W-
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U
0.15 (0.006) T
-V-
14X REF
K
N
N
TSSOP-14
DTB SUFFIX
CASE 948G-01
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
---
1.20
---
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.50
0.60
0.020
0.024
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0
8
0
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
_
_
_
_
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
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Phone: 81-3-5773-3850
MC34071/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
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Email: orderlit@onsemi.com
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Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
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