MC74AC157
Semiconductor Components Industries, LLC, 2001
May, 2001 Rev. 5
1
Publication Order Number:
MC74AC157/D
MC74AC157, MC74ACT157
Quad 2-Input Multiplexer
The MC74AC157/74ACT157 is a highspeed quad 2input
multiplexer. Four bits of data from two sources can be selected using
the common Select and Enable inputs. The four outputs present the
selected data in the true (noninverted) form.
The MC74AC157/74ACT157 can also be used as a function
generator.
Outputs Source/Sink 24 mA
ACT157 Has TTL Compatible Inputs
15
16
14
13
12
11
10
2
1
3
4
5
6
7
VCC
9
8
E
I0c
I1c
Zc
I0d
I1d
Zd
S
I0a
I1a
Za
I0b
I1b
Zb GND
Figure 1. Pinout: 16Lead Packages Conductors
(Top View)
PIN NAME
PIN
FUNCTION
I0aI0d
Source 0 Data Inputs
I1aI1d
Source 1 Data Inputs
E
Enable Input
S
Select Input
ZaZd
Outputs
TRUTH TABLE
Inputs
Outputs
E
S
I0
I1
Z
H
X
X
X
L
L
H
X
L
L
L
H
X
H
H
L
L
L
X
L
L
L
H
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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DIP16
N SUFFIX
CASE 648
1
16
SO16
D SUFFIX
CASE 751B
1
16
Device
Package
Shipping
ORDERING INFORMATION
MC74AC157N
PDIP16
25 Units/Rail
MC74AC157D
SOIC16
48 Units/Rail
MC74AC157DR2
2500 Tape & Reel
TSSOP16
DT SUFFIX
CASE 948F
MC74AC157DT
TSSOP16
96 Units/Rail
MC74AC157DTR2
TSSOP16
SOIC16
2500 Tape & Reel
MC74ACT157N
PDIP16
25 Units/Rail
MC74ACT157D
SOIC16
48 Units/Rail
MC74ACT157DR2
2500 Tape & Reel
MC74ACT157DT
TSSOP16
96 Units/Rail
MC74ACT157DTR2 TSSOP16
SOIC16
2500 Tape & Reel
1
16
See general marking information in the device marking
section on page 6 of this data sheet.
DEVICE MARKING INFORMATION
1
16
EIAJ16
M SUFFIX
CASE 966
MC74AC157M
EIAJ16
MC74AC157MEL
EIAJ16
2000 Tape & Reel
MC74ACT157M
EIAJ16
MC74ACT157MEL
EIAJ16
2000 Tape & Reel
50 Units/Rail
50 Units/Rail
MC74AC157, MC74ACT157
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2
Figure 2. Logic Symbol
S
E I0a I1a I0b I1b
Zb
I0c I1c I0d I1d
Za
Zc
Zd
FUNCTIONAL DESCRIPTION
The MC74AC157/74ACT157 is a quad 2input
multiplexer. It selects four bits of data from two sources
under the control of a common Select input (S). The Enable
input (E) is activeLOW. When E is HIGH, all of the
outputs (Z) are forced LOW regardless of all other inputs.
The MC74AC157/74ACT157 is the logic implementation
of a 4pole, 2position switch where the position of the
switch is determined by the logic levels supplied to the
Select input. The logic equations for the outputs are shown
below:
Za = E
(I1a
S+I0a
S)
Zb = E
(I1b
S+I0b
S)
Zc = E
(I1c
S+I0c
S)
Zd = E
(I1d
S+I0d
S)
A common use of the MC74AC157/74ACT157 is the
moving of data from two groups of registers to four
common output busses. The particular register from which
the data comes is determined by the state of the Select
input. A less obvious use is as a function generator. The
MC74AC157/74ACT157 can generate any four of the
sixteen different functions of two variables with one
variable common. This is useful for implementing gating
functions.
Figure 3. Logic Diagram
I0a
I1a
I0b
I1b
I0c
I1c
I0d
I1d
E
S
Za
NOTE:
This diagram is provided only for the understanding of logic operations
and should not be used to estimate propagation delays.
Zb
Zc
Zd
MC74AC157, MC74ACT157
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3
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
20
mA
IOUT
DC Output Sink/Source Current, per Pin
50
mA
ICC
DC VCC or GND Current per Output Pin
50
mA
Tstg
Storage Temperature
65 to +150
C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-
mended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
V
Supply Voltage
AC
2.0
5.0
6.0
V
VCC
Supply Voltage
ACT
4.5
5.0
5.5
V
VIN, VOUT
DC Input Voltage, Output Voltage (Ref. to GND)
0
VCC
V
VCC @ 3.0 V
150
tr, tf
Input Rise and Fall Time (Note 1)
AC Devices except Schmitt Inputs
VCC @ 4.5 V
40
ns/V
r, f
AC Devices except Schmitt Inputs
VCC @ 5.5 V
25
t tf
Input Rise and Fall Time (Note 2)
VCC @ 4.5 V
10
ns/V
tr, tf
In ut Rise and Fall Time (Note 2)
ACT Devices except Schmitt Inputs
VCC @ 5.5 V
8.0
ns/V
TJ
Junction Temperature (PDIP)
140
C
TA
Operating Ambient Temperature Range
40
25
85
C
IOH
Output Current High
24
mA
IOL
Output Current Low
24
mA
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
MC74AC157, MC74ACT157
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4
DC CHARACTERISTICS
74AC
74AC
Symbol
Parameter
VCC
(V)
TA = +25
C
TA =
40
C to
+85
C
Unit
Conditions
Typ
Guaranteed Limits
VIH
Minimum High Level
3.0
1.5
2.1
2.1
VOUT = 0.1 V
g
Input Voltage
4.5
2.25
3.15
3.15
V
or VCC 0.1 V
5.5
2.75
3.85
3.85
VIL
Maximum Low Level
3.0
1.5
0.9
0.9
VOUT = 0.1 V
Input Voltage
4.5
2.25
1.35
1.35
V
or VCC 0.1 V
5.5
2.75
1.65
1.65
VOH
Minimum High Level
3.0
2.99
2.9
2.9
IOUT = 50
A
g
Output Voltage
4.5
4.49
4.4
4.4
V
5.5
5.49
5.4
5.4
*VIN = VIL or VIH
3.0
2.56
2.46
V
12 mA
4.5
3.86
3.76
V
IOH
24 mA
5.5
4.86
4.76
24 mA
VOL
Maximum Low Level
3.0
0.002
0.1
0.1
IOUT = 50
A
Output Voltage
4.5
0.001
0.1
0.1
V
5.5
0.001
0.1
0.1
*VIN = VIL or VIH
3.0
0.36
0.44
V
12 mA
4.5
0.36
0.44
V
IOL
24 mA
5.5
0.36
0.44
24 mA
IIN
Maximum Input
5 5
0 1
1 0
A
VI = VCC GND
Leakage Current
5.5
0.1
1.0
A
VI = VCC, GND
IOLD
Minimum Dynamic
O t
t C
t
5.5
75
mA
VOLD = 1.65 V Max
IOHD
Output Current
5.5
75
mA
VOHD = 3.85 V Min
ICC
Maximum Quiescent
5 5
8 0
80
A
VIN = VCC or GND
Q
Supply Current
5.5
8.0
80
A
VIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
MC74AC157, MC74ACT157
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5
AC CHARACTERISTICS
(For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
Symbol
Parameter
VCC*
(V)
TA = +25
C
CL = 50 pF
TA = 40
C
to +85
C
CL = 50 pF
Unit
Fig.
No.
Min
Typ
Max
Min
Max
tPLH
Propagation Delay
3.3
1.5
7.0
11.5
1.5
13.0
ns
36
tPLH
g
y
S to Zn
5.0
1.5
5.5
9.0
1.5
10.0
ns
36
tPHL
Propagation Delay
3.3
1.5
6.5
11.0
1.5
12.0
ns
36
tPHL
g
y
S to Zn
5.0
1.5
5.0
8.5
1.0
9.5
ns
36
tPLH
Propagation Delay
3.3
1.5
7.0
11.5
1.5
13.0
ns
36
tPLH
g
y
E to Zn
5.0
1.5
5.5
9.0
1.5
10.0
ns
36
tPHL
Propagation Delay
3.3
1.5
6.5
11.0
1.5
12
ns
36
tPHL
g
y
En to Zn
5.0
1.5
5.5
9.0
1.0
9.5
ns
36
tPLH
Propagation Delay
3.3
1.5
5.0
8.5
1.0
9.0
ns
35
tPLH
g
y
In to Zn
5.0
1.5
4.0
6.5
1.0
7.0
ns
35
tPHL
Propagation Delay
3.3
1.5
5.0
8.0
1.0
9.0
ns
35
tPHL
g
y
In to Zn
5.0
1.5
4.0
6.5
1.0
7.0
ns
35
*Voltage Range 3.3 V is 3.3 V
0.3 V.
*Voltage Range 5.0 V is 5.0 V
0.5 V.
DC CHARACTERISTICS
74ACT
74ACT
Symbol
Parameter
VCC
(V)
TA = +25
C
TA =
40
C to
+85
C
Unit
Conditions
Typ
Guaranteed Limits
VIH
Minimum High Level
4.5
1.5
2.0
2.0
V
VOUT = 0.1 V
g
Input Voltage
5.5
1.5
2.0
2.0
V
or VCC 0.1 V
VIL
Maximum Low Level
4.5
1.5
0.8
0.8
V
VOUT = 0.1 V
Input Voltage
5.5
1.5
0.8
0.8
V
or VCC 0.1 V
VOH
Minimum High Level
4.5
4.49
4.4
4.4
V
IOUT = 50
A
g
Output Voltage
5.5
5.49
5.4
5.4
V
*VIN = VIL or VIH
4.5
3.86
3.76
V
IOH
24 mA
5.5
4.86
4.76
IOH
24 mA
VOL
Maximum Low Level
4.5
0.001
0.1
0.1
V
IOUT = 50
A
Output Voltage
5.5
0.001
0.1
0.1
V
*VIN = VIL or VIH
4.5
0.36
0.44
V
IOL
24 mA
5.5
0.36
0.44
IOL
24 mA
IIN
Maximum Input
5 5
0 1
1 0
A
VI = VCC GND
Leakage Current
5.5
0.1
1.0
A
VI = VCC, GND
ICCT
Additional Max. ICC/Input
5.5
0.6
1.5
mA
VI = VCC 2.1 V
IOLD
Minimum Dynamic
O t
t C
t
5.5
75
mA
VOLD = 1.65 V Max
IOHD
Output Current
5.5
75
mA
VOHD = 3.85 V Min
ICC
Maximum Quiescent
5 5
8 0
80
A
VIN = VCC or GND
Q
Supply Current
5.5
8.0
80
A
VIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
Maximum test duration 2.0 ms, one output loaded at a time.
MC74AC157, MC74ACT157
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6
AC CHARACTERISTICS
(For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
Symbol
Parameter
VCC*
(V)
TA = +25
C
CL = 50 pF
TA = 40
C
to +85
C
CL = 50 pF
Unit
Fig.
No.
Min
Typ
Max
Min
Max
tPLH
Propagation Delay
5 0
2 0
9 0
1 5
10 0
ns
36
tPLH
Pro agation Delay
S to Zn
5.0
2.0
9.0
1.5
10.0
ns
36
tPHL
Propagation Delay
5 0
2 0
9 5
2 0
10 5
ns
36
tPHL
Pro agation Delay
S to Zn
5.0
2.0
9.5
2.0
10.5
ns
36
tPLH
Propagation Delay
5 0
1 5
10
1 5
11 5
ns
36
tPLH
Pro agation Delay
En to Zn
5.0
1.5
10
1.5
11.5
ns
36
tPHL
Propagation Delay
5 0
1 5
8 5
1 0
9 0
ns
36
tPHL
Pro agation Delay
En to Zn
5.0
1.5
8.5
1.0
9.0
ns
36
tPLH
Propagation Delay
5 0
1 5
7 0
1 0
8 5
ns
35
tPLH
Pro agation Delay
In to Zn
5.0
1.5
7.0
1.0
8.5
ns
35
tPHL
Propagation Delay
5 0
1 5
7 5
1 0
8 5
ns
35
tPHL
Pro agation Delay
In to Zn
5.0
1.5
7.5
1.0
8.5
ns
35
*Voltage Range 5.0 V is 5.0 V
0.5 V.
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
50
pF
VCC = 5.0 V
MARKING DIAGRAMS
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
AC157
AWLYWW
MC74AC157N
AWLYYWW
AC
157
ALYW
ACT157
AWLYWW
ACT
157
ALYW
MC74ACT157N
AWLYYWW
DIP16
SO16
TSSOP16
EIAJ16
74AC157
ALYW
74ACT157
ALYW
MC74AC157, MC74ACT157
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7
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1
8
9
16
K
PLANE
T
M
A
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.740
0.770
18.80
19.55
B
0.250
0.270
6.35
6.85
C
0.145
0.175
3.69
4.44
D
0.015
0.021
0.39
0.53
F
0.040
0.70
1.02
1.77
G
0.100 BSC
2.54 BSC
H
0.050 BSC
1.27 BSC
J
0.008
0.015
0.21
0.38
K
0.110
0.130
2.80
3.30
L
0.295
0.305
7.50
7.74
M
0
10
0
10
S
0.020
0.040
0.51
1.01
_
_
_
_
PDIP16
N SUFFIX
16 PIN PLASTIC DIP PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
16
9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PL
P
B
A
M
0.25 (0.010)
B
S
T
D
K
C
16 PL
S
B
M
0.25 (0.010)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
SO16
D SUFFIX
16 PIN PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
MC74AC157, MC74ACT157
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8
PACKAGE DIMENSIONS
TSSOP16
DT SUFFIX
16 PIN PLASTIC TSSOP PACKAGE
CASE948F01
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
---
1.20
---
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.18
0.28
0.007
0.011
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0
8
0
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
_
_
_
_
SECTION NN
SEATING
PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X
L/2
U
S
U
0.15 (0.006) T
S
U
0.15 (0.006) T
S
U
M
0.10 (0.004)
V
S
T
0.10 (0.004)
T
V
W
0.25 (0.010)
16X REF
K
N
N
EIAJ16
M SUFFIX
16 PIN PLASTIC EIAJ PACKAGE
CASE96601
ISSUE O
HE
A1
DIM
MIN
MAX
MIN
MAX
INCHES
---
2.05
---
0.081
MILLIMETERS
0.05
0.20
0.002
0.008
0.35
0.50
0.014
0.020
0.18
0.27
0.007
0.011
9.90
10.50
0.390
0.413
5.10
5.45
0.201
0.215
1.27 BSC
0.050 BSC
7.40
8.20
0.291
0.323
0.50
0.85
0.020
0.033
1.10
1.50
0.043
0.059
0
0.70
0.90
0.028
0.035
---
0.78
---
0.031
A1
HE
Q1
LE
_
10
_
0
_
10
_
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN PROTRUSIONS AND
ADJACENT LEAD TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005)
0.10 (0.004)
1
16
9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
MC74AC157, MC74ACT157
http://onsemi.com
9
Notes
MC74AC157, MC74ACT157
http://onsemi.com
10
Notes
MC74AC157, MC74ACT157
http://onsemi.com
11
Notes
MC74AC157, MC74ACT157
http://onsemi.com
12
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
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MC74AC157/D
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