Semiconductor Components Industries, LLC, 2001
May, 2001 Rev. 5
1
Publication Order Number:
MC74AC74/D
MC74AC74, MC74ACT74
Dual D-Type Positive
Edge-Triggered Flip-Flop
The MC74AC74/74ACT74 is a dual Dtype flipflop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is locked out and
information present will not be transferred to the outputs until the
next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
Outputs Source/Sink 24 mA
ACT74 Has TTL Compatible Inputs
CP1
CD2
CP2
13
14
12
11
10
9
8
2
1
3
4
5
6
7
VCC
CD1
D1
CP1 SD1 Q1
Q1
CD2 D2
CP2 SD2 Q2
Q2
CD1
SD1
Q1
D1
SD2
Q2
Q2
D2
GND
Q1
Figure 1. Pinout: 14Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
FUNCTION
D1, D2
Data Inputs
CP1, CP2
Clock Pulse Inputs
CD1, CD2
Direct Clear Inputs
SD1, SD2
Direct Set Inputs
Q1, Q1, Q2, Q2
Outputs
TSSOP14
DT SUFFIX
CASE 948G
1
14
EIAJ14
M SUFFIX
CASE 965
1
14
SO14
D SUFFIX
CASE 751A
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1
14
1
14
PDIP14
N SUFFIX
CASE 646
Device
Package
Shipping
ORDERING INFORMATION
MC74AC74DT
TSSOP14
96 Units/Rail
MC74AC74DTR2
TSSOP14 2500 Tape & Reel
MC74ACT74DT
TSSOP14
96 Units/Rail
MC74ACT74DTR2
TSSOP14 2500 Tape & Reel
MC74AC74N
PDIP14
25 Units/Rail
MC74AC74D
SOIC14
55 Units/Rail
MC74ACT74N
PDIP14
25 Units/Rail
MC74AC74DR2
SOIC14
2500 Tape & Reel
MC74ACT74D
SOIC14
55 Units/Rail
MC74ACT74DR2
SOIC14
2500 Tape & Reel
MC74AC74M
EIAJ14
50 Units/Rail
MC74AC74MEL
EIAJ14
2000 Tape & Reel
MC74ACT74M
EIAJ14
50 Units/Rail
MC74ACT74MEL
EIAJ14
2000 Tape & Reel
See general marking information in the device marking
section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
MC74AC74, MC74ACT74
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2
TRUTH TABLE (Each Half)
Inputs
Outputs
SD
CD
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
NOTE:
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial;
= LOW-to-HIGH Clock Transition
Q0(Q0) = Previous Q(Q) before LOW-to-HIGH
Transition of Clock
Figure 2. Logic Symbol
SD1
Q1
CP1
Q1
CD1
SD2
Q2
D2 CP2
Q2
CD2
D1
SD
D
CP
CD
Q
Q
Figure 3. Logic Diagram
NOTE:
This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to +7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC +0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC +0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Sink/Source Current, per Pin
50
mA
ICC
DC VCC or GND Current per Output Pin
50
mA
Tstg
Storage Temperature
65 to +150
C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-
mended Operating Conditions.
MC74AC74, MC74ACT74
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3
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
V
Supply Voltage
AC
2.0
5.0
6.0
V
VCC
Supply Voltage
ACT
4.5
5.0
5.5
V
Vin, Vout
DC Input Voltage, Output Voltage (Ref. to GND)
0
VCC
V
VCC @ 3.0 V
150
tr, tf
Input Rise and Fall Time (Note )
AC Devices except Schmitt Inputs
VCC @ 4.5 V
40
ns/V
r, f
AC Devices except Schmitt Inputs
VCC @ 5.5 V
25
t tf
Input Rise and Fall Time (Note )
VCC @ 4.5 V
10
ns/V
tr, tf
In ut Rise and Fall Time (Note )
ACT Devices except Schmitt Inputs
VCC @ 5.5 V
8.0
ns/V
TJ
Junction Temperature (PDIP)
140
C
TA
Operating Ambient Temperature Range
40
25
85
C
IOH
Output Current High
24
mA
IOL
Output Current Low
24
mA
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
74AC
74AC
Symbol
Parameter
VCC
(V)
TA = +25
C
TA =
40
C to
+85
C
Unit
Conditions
Typ
Guaranteed Limits
VIH
Minimum High Level
3.0
1.5
2.1
2.1
VOUT = 0.1 V
g
Input Voltage
4.5
2.25
3.15
3.15
V
or VCC 0.1 V
5.5
2.75
3.85
3.85
VIL
Maximum Low Level
3.0
1.5
0.9
0.9
VOUT = 0.1 V
Input Voltage
4.5
2.25
1.35
1.35
V
or VCC 0.1 V
5.5
2.75
1.65
1.65
VOH
Minimum High Level
3.0
2.99
2.9
2.9
IOUT = 50
A
g
Output Voltage
4.5
4.49
4.4
4.4
V
5.5
5.49
5.4
5.4
*VIN = VIL or VIH
3.0
2.56
2.46
V
12 mA
4.5
3.86
3.76
V
IOH
24 mA
5.5
4.86
4.76
24 mA
VOL
Maximum Low Level
3.0
0.002
0.1
0.1
IOUT = 50
A
Output Voltage
4.5
0.001
0.1
0.1
V
5.5
0.001
0.1
0.1
*VIN = VIL or VIH
3.0
0.36
0.44
V
12 mA
4.5
0.36
0.44
V
IOL
24 mA
5.5
0.36
0.44
24 mA
IIN
Maximum Input
5 5
0 1
1 0
A
VI = VCC GND
Leakage Current
5.5
0.1
1.0
A
VI = VCC, GND
IOLD
Minimum Dynamic
O t
t C
t
5.5
75
mA
VOLD = 1.65 V Max
IOHD
Output Current
5.5
75
mA
VOHD = 3.85 V Min
ICC
Maximum Quiescent
5 5
4 0
40
A
VIN = VCC or GND
Q
Supply Current
5.5
4.0
40
A
VIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
MC74AC74, MC74ACT74
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4
AC CHARACTERISTICS
(For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
Symbol
Parameter
VCC*
(V)
TA = +25
C
CL = 50 pF
TA = 40
C
to +85
C
CL = 50 pF
Unit
Fig.
No.
Min
Typ
Max
Min
Max
fmax
Maximum Clock
3.3
100
125
95
MHz
33
fmax
Frequency
5.0
140
160
125
MHz
33
tPLH
Propagation Delay
3.3
5.0
8.0
12.5
4.0
13.0
ns
36
tPLH
g
y
CDn or SDn to Qn or Qn
5.0
3.5
6.0
9.0
3.0
10.0
ns
36
tPHL
Propagation Delay
3.3
4.0
10.5
12.0
3.5
13.5
ns
36
tPHL
g
y
CDn or SDn to Qn or Qn
5.0
3.0
8.0
9.5
2.5
10.5
ns
36
tPLH
Propagation Delay
3.3
4.5
8.0
13.5
4.0
16.0
ns
36
tPLH
g
y
CPn to Qn or Qn
5.0
3.5
6.0
10.0
3.0
10.5
ns
36
tPHL
Propagation Delay
3.3
3.5
8.0
14.0
3.5
14.5
ns
36
tPHL
g
y
CPn to Qn or Qn
5.0
2.5
6.0
10.0
2.5
10.5
ns
36
*Voltage Range 3.3 V is 3.3 V
0.3 V.
Voltage Range 5.0 V is 5.0 V
0.5 V.
AC OPERATING REQUIREMENTS
74AC
74AC
Symbol
Parameter
VCC*
(V)
TA = +25
C
CL = 50 pF
TA = 40
C
to +85
C
CL = 50 pF
Unit
Fig.
No.
Typ
Guaranteed Minimum
ts
Set-up Time, HIGH or LOW
3.3
1.5
4.0
4.5
ns
39
ts
Dn to CPn
5.0
1.0
3.0
3.0
ns
39
th
Hold Time, HIGH or LOW
3.3
2.0
0.5
0.5
ns
39
th
Dn to CPn
5.0
1.5
0.5
0.5
ns
39
tw
CPn or CDn or SDn
3.3
3.0
5.5
7.0
ns
36
tw
Pulse Width
5.0
2.5
4.5
5.0
ns
36
trec
Recovery TIme
3.3
2.5
0
0
ns
39
trec
CDn or SDn to CP
5.0
2.0
0
0
ns
39
*Voltage Range 3.3 V is 3.3 V
0.3 V.
Voltage Range 5.0 V is 5.0 V
0.5 V.
MC74AC74, MC74ACT74
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5
DC CHARACTERISTICS
74ACT
74ACT
Symbol
Parameter
VCC
(V)
TA = +25
C
TA =
40
C to
+85
C
Unit
Conditions
Typ
Guaranteed Limits
VIH
Minimum High Level
4.5
1.5
2.0
2.0
V
VOUT = 0.1 V
g
Input Voltage
5.5
1.5
2.0
2.0
V
or VCC 0.1 V
VIL
Maximum Low Level
4.5
1.5
0.8
0.8
V
VOUT = 0.1 V
Input Voltage
5.5
1.5
0.8
0.8
V
or VCC 0.1 V
VOH
Minimum High Level
4.5
4.49
4.4
4.4
V
IOUT = 50
A
g
Output Voltage
5.5
5.49
5.4
5.4
V
*VIN = VIL or VIH
4.5
3.86
3.76
V
IOH
24 mA
5.5
4.86
4.76
IOH
24 mA
VOL
Maximum Low Level
4.5
0.001
0.1
0.1
V
IOUT = 50
A
Output Voltage
5.5
0.001
0.1
0.1
V
*VIN = VIL or VIH
4.5
0.36
0.44
V
IOL
24 mA
5.5
0.36
0.44
IOL
24 mA
IIN
Maximum Input
5 5
0 1
1 0
A
VI = VCC GND
Leakage Current
5.5
0.1
1.0
A
VI = VCC, GND
ICCT
Additional Max. ICC/Input
5.5
0.6
1.5
mA
VI = VCC 2.1 V
IOLD
Minimum Dynamic
O t
t C
t
5.5
75
mA
VOLD = 1.65 V Max
IOHD
Output Current
5.5
75
mA
VOHD = 3.85 V Min
ICC
Maximum Quiescent
5 5
4 0
40
A
VIN = VCC or GND
Q
Supply Current
5.5
4.0
40
A
VIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS
(For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
Symbol
Parameter
VCC*
(V)
TA = +25
C
CL = 50 pF
TA = 40
C
to +85
C
CL = 50 pF
Unit
Fig.
No.
Min
Typ
Max
Min
Max
fmax
Maximum Clock
5 0
145
210
125
MHz
33
fmax
Maximum Clock
Frequency
5.0
145
210
125
MHz
33
tPLH
Propagation Delay
5 0
3 0
5 5
9 5
2 5
10 5
ns
36
tPLH
Pro agation Delay
CDn or SDn to Qn or Qn
5.0
3.0
5.5
9.5
2.5
10.5
ns
36
tPHL
Propagation Delay
5 0
3 0
6 0
10 0
3 0
11 5
ns
36
tPHL
Pro agation Delay
CDn or SDn to Qn or Qn
5.0
3.0
6.0
10.0
3.0
11.5
ns
36
tPLH
Propagation Delay
5 0
4 0
7 5
11 0
4 0
13 0
ns
36
tPLH
Pro agation Delay
CPn to Qn or Qn
5.0
4.0
7.5
11.0
4.0
13.0
ns
36
tPHL
Propagation Delay
5 0
3 5
6 0
10 0
3 0
11 5
ns
36
tPHL
Pro agation Delay
CPn to Qn or Qn
5.0
3.5
6.0
10.0
3.0
11.5
ns
36
*Voltage Range 5.0 V is 5.0 V
0.5 V.
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