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Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 1
1
Publication Order Number:
MC74HC164A/D
MC74HC164A
8-Bit Serial-Input/
Parallel-Output Shift
Register
HighPerformance SiliconGate CMOS
The MC74HC164A is identical in pinout to the LS164. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The MC74HC164A is an 8bit, serialinput to paralleloutput shift
register. Two serial data inputs, A1 and A2, are provided so that one
input may be used as a data enable. Data is entered on each rising edge
of the clock. The activelow asynchronous Reset overrides the Clock
and Serial Data inputs.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAM
PIN 14 = VCC
PIN 7 = GND
3
QA
4
5
6
10
11
12
13
QB
QC
QD
QE
QF
QG
QH
PARALLEL
DATA
OUTPUTS
9
RESET
CLOCK
8
SERIAL
DATA
INPUTS
A1
A2
1
2
DATA
FUNCTION TABLE
Inputs
Outputs
Reset Clock
A1
A2 QA QB
...
QH
L
X
X
X
L
L
...
L
H
X
X
No Change
H
H
D
D QAn
...
QGn
H
D
H
D QAn
...
QGn
D = data input
QAn QGn = data shifted from the preceding
stage on a rising edge at the clock input.
Device
Package
Shipping
ORDERING INFORMATION
MC74HC164AN
PDIP14
2000 / Box
MC74HC164AD
SOIC14
http://onsemi.com
55 / Rail
MC74HC164ADR2
SOIC14
2500 / Reel
MARKING
DIAGRAMS
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
MC74HC164ADT
TSSOP14
96 / Rail
MC74HC164ADTR2
TSSOP14
2500 / Reel
TSSOP14
DT SUFFIX
CASE 948G
HC
164A
ALYW
1
14
1
14
PDIP14
N SUFFIX
CASE 646
MC74HC164AN
AWLYYWW
SOIC14
D SUFFIX
CASE 751A
1
14
HC164A
AWLYWW
PIN ASSIGNMENT
11
12
13
14
8
9
10
5
4
3
2
1
7
6
QE
QF
QG
QH
VCC
CLOCK
RESET
QB
QA
A2
A1
GND
QD
QC
MC74HC164A
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2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
50
mA
PD
Power Dissipation in Still Air,
Plastic DIP
SOIC Package
TSSOP Package
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55
_
C to
25
_
C
v
85
_
C
v
125
_
C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout|
v
2.4 mA
|Iout|
v
4.0 mA
|Iout|
v
5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC164A
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3
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Unit
Guaranteed Limit
VCC
V
Test Conditions
Parameter
Symbol
Unit
v
125
_
C
v
85
_
C
55
_
C to
25
_
C
VCC
V
Test Conditions
Parameter
Symbol
VOL
Maximum LowLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout|
v
2.4 mA
|Iout|
v
4.0 mA
|Iout|
v
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin
Maximum Input Leakage
Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
4
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
55
_
C to
25
_
C
v
85
_
C
v
125
_
C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
10
20
40
50
10
20
35
45
10
20
30
40
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
160
100
32
27
200
150
40
34
250
200
48
42
ns
tPHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
175
100
35
30
220
150
44
37
260
200
53
45
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin
Maximum Input Capacitance
--
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
Typical @ 25
C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
180
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
MC74HC164A
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4
TIMING REQUIREMENTS
(Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
55
_
C to
25
_
C
v
85
_
C
v
125
_
C
Unit
tsu
Minimum Setup Time, A1 or A2 to Clock
(Figure 3)
2.0
3.0
4.5
6.0
25
15
7
5
35
20
8
6
40
25
9
6
ns
th
Minimum Hold Time, Clock to A1 or A2
(Figure 3)
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
50
26
12
10
60
35
15
12
75
45
20
15
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
50
26
12
10
60
35
15
12
75
45
20
15
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book
(DL129/D).
MC74HC164A
http://onsemi.com
5
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 1, 2)
Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A1 and
A2 inputs must be high, thereby allowing one input to be
used as a dataenable input. When only one serial input is
used, the other must be connected to VCC.
Clock (Pin 8)
Shift Register Clock. A positivegoing transition on this
pin shifts the data at each stage to the next stage. The shift
register is completely static, allowing clock rates down to
DC in a continuous or intermittent mode.
OUTPUTS
QA QH (Pins 3, 4, 5, 6, 10, 11, 12, 13)
Parallel Shift Register Outputs. The shifted data is
presented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)
ActiveLow, Asynchronous Reset Input. A low voltage
applied to this input resets all internal flipflops and sets
Outputs QA QH to the low level state.
SWITCHING WAVEFORMS
tf
VCC
GND
90%
50%
10%
tw
tPLH
tPHL
CLOCK
Q
tTLH
tTHL
Figure 1.
RESET
trec
Figure 2.
tr
1/fmax
90%
50%
10%
VCC
GND
VCC
GND
Q
CLOCK
50%
50%
50%
tPHL
tw
A1 OR A2
Figure 3.
VCC
GND
VCC
GND
50%
50%
CLOCK
tsu
th
VALID
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
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