Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 8
1
Publication Order Number:
MC74HC244A/D
MC74HC244A
Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver
HighPerformance SiliconGate CMOS
The MC74HC244A is identical in pinout to the LS244. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed
to be used with 3state memory address drivers, clock drivers, and
other busoriented systems. The device has noninverting outputs and
two activelow output enables.
The HC244A is similar in function to the HC240A.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 136 FETs or 34 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
A1
A2
A3
A4
B1
B2
B3
B4
17
15
13
11
8
6
4
2
18
16
14
12
9
7
5
3
YB4
YB3
YB2
YB1
YA4
YA3
YA2
YA1
NONINVERTING
OUTPUTS
PIN 20 = VCC
PIN 10 = GND
OUTPUT
ENABLES
ENABLE A
ENABLE B
1
19
FUNCTION TABLE
Inputs
Outputs
Enable A,
Enable B
A, B
YA, YB
L
L
L
L
H
H
H
X
Z
Z = high impedance
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MARKING
DIAGRAMS
1
20
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
SOIC WIDE20
DW SUFFIX
CASE 751D
HC244A
AWLYYWW
PDIP20
N SUFFIX
CASE 738
1
20
MC74HC244AN
AWLYYWW
TSSOP20
DT SUFFIX
CASE 948G
1
20
1
20
1
20
Device
Package
Shipping
ORDERING INFORMATION
MC74HC244AN
PDIP20
1440 / Box
MC74HC244ADW
SOICWIDE
38 / Rail
MC74HC244ADWR2
SOICWIDE
1000 / Reel
MC74HC244ADT
TSSOP20
75 / Rail
MC74HC244ADTR2
TSSOP20
2500 / Reel
HC
244A
ALYW
1
20
PIN ASSIGNMENT
A3
A2
YB4
A1
ENABLE A
GND
YB1
A4
YB2
YB3
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
YA2
B4
YA1
ENABLE B
VCC
B1
YA4
B2
YA3
B3
MC74HC244A
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2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
35
mA
ICC
DC Supply Current, VCC and GND Pins
75
mA
PD
Power Dissipation in Still Air,
Plastic DIP
SOIC Package
TSSOP Package
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = VCC 0.1 V
|Iout|
v
20
A
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V
|Iout|
v
20
A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH
|Iout|
v
2.4 mA
|Iout|
v
6.0 mA
|Iout|
v
7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
VOL
Maximum LowLevel Output
Voltage
Vin = VIL
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIL
|Iout|
v
2.4 mA
|Iout|
v
6.0 mA
|Iout|
v
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC244A
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3
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Unit
v
125
_
C
v
85
_
C
55 to
25
_
C
VCC
V
Test Conditions
Parameter
Symbol
Iin
Maximum Input Leakage
Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
IOZ
Maximum ThreeState
Leakage Current
Output in HighImpedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
0.5
5.0
10
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
4.0
40
160
A
NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
tPLH,
tPHL
Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)
2.0
3.0
4.5
6.0
96
50
18
15
115
60
23
20
135
70
27
23
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
60
22
19
140
70
28
24
165
80
33
28
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
60
22
19
140
70
28
24
165
80
33
28
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
Cin
Maximum Input Capacitance
--
10
10
10
pF
Cout
Maximum ThreeState Output Capacitance (Output in
HighImpedance State)
--
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D).
Typical @ 25
C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Buffer)*
34
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
MC74HC244A
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4
SWITCHING WAVEFORMS
Figure 1.
Figure 2.
VCC
GND
tf
tr
DATA INPUT
A OR B
OUTPUT
YA OR YB
10%
50%
90%
10%
50%
90%
tTLH
tPLH
tPHL
tTHL
ENABLE
A OR B
OUTPUT Y
OUTPUT Y
50%
50%
50%
90%
10%
tPZL
tPLZ
tPZH
tPHZ
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
TEST CIRCUITS
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3. Test Circuit
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 k
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, B1, B2, B3, B4
(Pins 2, 4, 6, 8, 11, 13, 15, 17)
Data input pins. Data on these pins appear in noninverted
form on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
Enable A, Enable B (Pins 1, 19)
Output enables (activelow). When a low level is applied
to these pins, the outputs are enabled and the devices
function as noninverting buffers. When a high level is
applied, the outputs assume the high impedance state.
OUTPUTS
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)
Device outputs. Depending upon the state of the
outputenable pins, these outputs are either noninverting
outputs or highimpedance outputs.
MC74HC244A
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5
LOGIC DETAIL
DATA
INPUT
A OR B
ENABLE A OR
ENABLE B
TO THREE OTHER
A OR B INVERTERS
ONE OF 8
INVERTERS
YA
OR
YB
VCC
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