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Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 8
1
Publication Order Number:
MC74HC373A/D
MC74HC373A
Octal 3-State Non-Inverting
Transparent Latch
HighPerformance SiliconGate CMOS
The MC74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
highimpedance state. Thus, data may be latched even when the
outputs are not enabled.
The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
The HC373A is the noninverting version of the HC533A.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 186 FETs or 46.5 Equivalent Gates
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MARKING
DIAGRAMS
1
20
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
SOIC WIDE20
DW SUFFIX
CASE 751D
HC373A
AWLYYWW
PDIP20
N SUFFIX
CASE 738
1
20
MC74HC373AN
AWLYYWW
TSSOP20
DT SUFFIX
CASE 948G
1
20
1
20
1
20
Device
Package
Shipping
ORDERING INFORMATION
MC74HC373AN
PDIP20
1440 / Box
MC74HC373ADW
SOICWIDE
38 / Rail
MC74HC373ADWR2
SOICWIDE
1000 / Reel
MC74HC373ADT
TSSOP20
75 / Rail
MC74HC373ADTR2
TSSOP20
2500 / Reel
HC
373A
ALYW
1
20
MC74HC373A
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2
LOGIC DIAGRAM
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
OUTPUT ENABLE
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
PIN 20 = VCC
PIN 10 = GND
NONINVERTING
OUTPUTS
11
LATCH ENABLE
FUNCTION TABLE
Inputs
Output
Output
Latch
Enable
Enable
D
Q
L
H
H
H
L
H
L
L
L
L
X
No Change
H
X
X
Z
X = Don't Care
Z = High Impedance
PIN ASSIGNMENT
Q2
D1
D0
Q0
OUTPUT
ENABLE
GND
Q3
D3
D2
Q1
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
VCC
LATCH
ENABLE
Q4
D4
D5
Q5
Design Criteria
Value
Units
Internal Gate Count*
46.5
ea
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
W
Speed Power Product
0.0075
pJ
*Equivalent to a twoinput NAND gate.
MC74HC373A
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3
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
35
mA
ICC
DC Supply Current, VCC and GND Pins
75
mA
PD
Power Dissipation in Still Air,
Plastic DIP
SOIC Package
TSSOP Package
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = VCC 0.1 V
|Iout|
v
20
A
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V
|Iout|
v
20
A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH
|Iout|
v
2.4 mA
|Iout|
v
6.0 mA
|Iout|
v
7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
VOL
Maximum LowLevel Output
Voltage
Vin = VIL
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIL
|Iout|
v
2.4 mA
|Iout|
v
6.0 mA
|Iout|
v
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC373A
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4
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Unit
v
125
_
C
v
85
_
C
55 to
25
_
C
VCC
V
Test Conditions
Parameter
Symbol
Iin
Maximum Input Leakage
Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
IOZ
Maximum ThreeState
Leakage Current
Output in HighImpedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
0.5
5.0
10
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
4.0
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
tPLH
tPHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
3.0
4.5
6.0
125
80
25
21
155
110
31
26
190
130
38
32
ns
tPLH
tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
3.0
4.5
6.0
140
90
28
24
175
120
35
30
210
140
42
36
ns
tPLZ
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum ThreeState Output Capacitance
(Output in HighImpedance State)
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D).
Typical @ 25
C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
36
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
MC74HC373A
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5
TIMING REQUIREMENTS
(CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
55 to 25
_
C
v
85
_
C
v
125
_
C
Symbol
Parameter
Fig.
VCC
Volts
Min
Max
Min
Max
Min
Max
Unit
tsu
Minimum Setup Time, Input D to Latch Enable
4
2.0
3.0
4.5
6.0
25
20
5.0
5.0
30
25
6.0
6.0
40
30
8.0
7.0
ns
th
Minimum Hold Time, Latch Enable to Input D
4
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5 0
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Latch Enable
2
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
1
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
SWITCHING WAVEFORMS
Figure 1.
Figure 2.
VCC
GND
tf
tr
INPUT D
Q
10%
50%
90%
10%
50%
90%
tTLH
tPLH
tPHL
tTHL
VCC
GND
50%
LATCH ENABLE
tPLH
tPHL
Q
tw
50%
Figure 3.
Figure 4.
50%
50%
1.3 V
Q
tPZL
tPLZ
tPZH tPHZ
10%
90%
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
Q
OUTPUT
ENABLE
50%
INPUT D
LATCH ENABLE
VCC
VCC
GND
GND
VALID
th
tsu
50%
MC74HC373A
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6
TEST CIRCUITS
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 5.
Figure 6.
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 k
EXPANDED LOGIC DIAGRAM
D0
3
D
Q
LE
2
Q0
11
1
D1
4
D
Q
LE
5
Q1
D2
7
D
Q
LE
6
Q2
D3
8
D
Q
LE
9
Q3
D4
13
D
Q
LE
12
Q4
D5
14
D
Q
LE
15
Q5
D6
17
D
Q
LE
16
Q6
D7
18
D
Q
LE
19
Q7
MC74HC373A
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7
PACKAGE DIMENSIONS
SO20
DW SUFFIX
CASE 751D05
ISSUE F
PDIP20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 73803
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
25.66
27.17
1.010
1.070
B
6.10
6.60
0.240
0.260
C
3.81
4.57
0.150
0.180
D
0.39
0.55
0.015
0.022
G
2.54 BSC
0.100 BSC
J
0.21
0.38
0.008
0.015
K
2.80
3.55
0.110
0.140
L
7.62 BSC
0.300 BSC
M
0
15
0
15
N
0.51
1.01
0.020
0.040
_
_
_
_
E
1.27
1.77
0.050
0.070
1
11
10
20
A
SEATING
PLANE
K
N
F
G
D
20 PL
T
M
A
M
0.25 (0.010)
T
E
B
C
F
1.27 BSC
0.050 BSC
20
1
11
10
B
20X
H
10X
C
L
18X
A1
A
SEATING
PLANE
q
h
X 45
_
E
D
M
0.25
M
B
M
0.25
S
A
S
B
T
e
T
B
A
DIM
MIN
MAX
MILLIMETERS
A
2.35
2.65
A1
0.10
0.25
B
0.35
0.49
C
0.23
0.32
D
12.65
12.95
E
7.40
7.60
e
1.27 BSC
H
10.05
10.55
h
0.25
0.75
L
0.50
0.90
q
0
7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
_
_
MC74HC373A
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8
PACKAGE DIMENSIONS
TSSOP20
DT SUFFIX
CASE 948E02
ISSUE A
DIM
A
MIN
MAX
MIN
MAX
INCHES
6.60
0.260
MILLIMETERS
B
4.30
4.50
0.169
0.177
C
1.20
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.27
0.37
0.011
0.015
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0 8 0 8
_
_
_
_
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4.
DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5.
DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6.
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7.
DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
1
10
11
20
PIN 1
IDENT
A
B
T
0.100 (0.004)
C
D
G
H
SECTION NN
K
K1
J J1
N
N
M
F
W
SEATING
PLANE
V
U
S
U
M
0.10 (0.004)
V
S
T
20X REF
K
L
L/2
2X
S
U
0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40
0.252
S
U
0.15 (0.006) T
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
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PUBLICATION ORDERING INFORMATION
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MC74HC373A/D
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