MC74VHC138
3-to-8 Line Decoder
The MC74VHC138 is an advanced high speed CMOS 3to8
decoder fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 A2)
determine which one of the outputs (Y0 Y7) will go Low. When
enable input E3 is held Low or either E2 or E1 is held High, decoding
function is inhibited and all outputs go high. E3, E2, and E1 inputs are
provided to ease cascade connection and for use as an address decoder
for memory systems.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
High Speed: t
PD
= 5.7ns (Typ) at V
CC
= 5V
Low Power Dissipation: I
CC
= 4
A (Max) at T
A
= 25
C
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 122 FETs or 30.5 Equivalent Gates
Semiconductor Components Industries, LLC, 2001
March, 2001 Rev. 3
1
Publication Order Number:
MC74VHC138/D
Device
Package
Shipping
ORDERING INFORMATION
MC74VHC138D
SOIC16
48 Units/Rail
MC74VHC138DR2
SOIC16
http://onsemi.com
2500 Units/Reel
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
SOIC EIAJ16
M SUFFIX
CASE 966
MARKING DIAGRAMS
1
8
9
16
1
8
16
9
1
16
9
8
VHC138
AWLYYWW
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
VHC
138
AWLYWW
VHC138
ALYW
MC74VHC138DT
TSSOP16
96 Units/Rail
MC74VHC138DTR2 TSSOP16
2500 Units/Reel
MC74VHC138M
SOIC
EIAJ16
48 Units/Rail
MC74VHC138MEL
SOIC
EIAJ16
2000 Units/Reel
A = Assembly Location
L
= Wafer Lot
Y = Year
W = Work Week
A
= Assembly Location
WL = Wafer Lot
Y
= Year
WW = Work Week
MC74VHC138
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2
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
A0
E1
A2
A1
Y7
E3
E2
GND
Y3
Y2
Y1
Y0
V
CC
Y5
Y4
Y6
7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
9
10
11
12
13
14
15
3
2
1
E3
E2
A0
A1
A2
ACTIVE-LOW
OUTPUTS
SELECT
INPUTS
E1
ENABLE
INPUTS
4
5
6
Inputs
Outputs
E3
E2
E1
A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
H
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
FUNCTION TABLE
H = high level (steady state); L = low level (steady state);
X = don't care
LOGIC DIAGRAM
MC74VHC138
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3
A0
A1
A2
E2
E1
E3
1
2
3
4
5
6
15
14
13
12
11
10
9
7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y0
EXPANDED LOGIC DIAGRAM
15
IEC LOGIC DIAGRAM
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
14
13
12
11
10
9
7
4
5
6
3
2
1
A0
A1
A2
E3
E2
E1
2
1
4
BIN/OCT
1
0
2
4
3
5
6
7
EN
&
15 Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
14
13
12
11
10
9
7
4
5
6
3
2
1
A0
A1
A2
E3
E2
E1
0
2
DMUX
1
0
2
4
3
5
6
7
&
G 0
7
MC74VHC138
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4
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage
0.5 to + 7.0
V
V
in
DC Input Voltage
0.5 to + 7.0
V
V
out
DC Output Voltage
0.5 to V
CC
+ 0.5
V
I
IK
Input Diode Current
20
mA
I
OK
Output Diode Current
20
mA
I
out
DC Output Current, per Pin
25
mA
I
CC
DC Supply Current, V
CC
and GND Pins
75
mA
P
D
Power Dissipation in Still Air,
SOIC Packages
TSSOP Package
500
450
mW
T
stg
Storage Temperature
65 to + 150
_
C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolutemaximumrated
conditions is not implied.
Derating -- SOIC Packages: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: 6.1 mW/
_
C from 65
_
to 125
_
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage
2.0
5.5
V
V
in
DC Input Voltage
0
5.5
V
V
out
DC Output Voltage
0
V
CC
V
T
A
Operating Temperature
55
+ 125
_
C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 3.3V
0.3V
V
CC
=5.0V
0.5V
0
0
100
20
ns/V
The
q
JA
of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and
figure below.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature
C
Time, Hours
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
1
1
10
100
1000
TIME, YEARS
NORMALIZED F
AILURE RA
TE
T J
= 80
C
T J
= 90
C
T J
= 100
C
T J
= 1
1
0
C
T J
= 130
C
T J
= 120
C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 1. Failure Rate vs. Time
Junction Temperature
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHC138
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5
DC ELECTRICAL CHARACTERISTICS
V
CC
T
A
= 25
C
T
A
=
85
C
T
A
=
125
C
Symbol
Parameter
Test Conditions
V
CC
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
V
IH
Minimum HighLevel
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
V
IL
Maximum
LowLevel Input
Voltage
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
V
OH
Minimum HighLevel
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= 50
A
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= 4 mA
I
OH
= 8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum
LowLevel Output
Voltage
V
V
or V
V
IN
= V
IH
or V
IL
I
OL
= 50
A
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
IN
Maximum Input
Leakage Current
V
IN
= 5.5 V or
GND
0 to
5.5
0.1
1.0
1.0
A
I
CC
Maximum Quiescent
Supply Current
V
IN
= V
CC
or GND
5.5
4.0
40.0
40.0
A
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3.0ns)
Symbo
T
A
= 25
C
T
A
= 40 to
85
C
T
A
= 55 to
125
C
Symbo
l
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Min
Max
Unit
t
PLH
,
t
PHL
Maximum
Propagation Delay,
A to Y
V
CC
= 3.3
0.3V
C
L
= 15pF
C
L
= 50pF
8.2
10.0
11.4
15.8
1.0
1.0
13.5
18.0
1.0
1.0
13.5
18.0
ns
A to Y
V
CC
= 5.0
0.5V
C
L
= 15pF
C
L
= 50pF
5.7
7.2
8.1
10.1
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
t
PLH
,
t
PHL
Maximum
Propagation Delay,
E3 to Y
V
CC
= 3.3
0.3V
C
L
= 15pF
C
L
= 50pF
8.1
10.6
12.8
16.3
1.0
1.0
15.0
18.5
1.0
1.0
15.0
18.5
ns
E3 to Y
V
CC
= 5.0
0.5V
C
L
= 15pF
C
L
= 50pF
5.6
7.1
8.1
10.1
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
t
PLH
,
t
PHL
Maximum
Propagation Delay,
E2 or E1 to Y
V
CC
= 3.3
0.3V
C
L
= 15pF
C
L
= 50pF
8.2
10.7
11.4
14.9
1.0
1.0
13.5
17.0
1.0
1.0
13.5
17.0
ns
E2 or E1 to Y
V
CC
= 5.0
0.5V
C
L
= 15pF
C
L
= 50pF
5.8
7.3
8.1
10.1
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
C
IN
Maximum Input
Capacitance
4
10
10
10
pF
Typical @ 25
C, V
CC
= 5.0V
C
PD
Power Dissipation Capacitance (Note 1.)
34
pF
1. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the noload dynamic
power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
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