Semiconductor Components Industries, LLC, 2000
November, 2000 Rev. 3
1
Publication Order Number:
MTD3055V/D
MTD3055V
Preferred Device
Power MOSFET
12 Amps, 60 Volts
NChannel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainSource Voltage
VDSS
60
Vdc
DrainGate Voltage (RGS = 1.0 M
)
VDGR
60
Vdc
GateSource Voltage
Continuous
Nonrepetitive (tp
10 ms)
VGS
VGSM
20
25
Vdc
Vpk
Drain Current Continuous @ 25
C
Drain Current
Continuous @ 100
C
Drain Current
Single Pulse (tp
10
s)
ID
ID
IDM
12
7.3
37
Adc
Apk
Total Power Dissipation @ 25
C
Derate above 25
C
Total Power Dissipation @ TA = 25
C, when
mounted to minimum recommended pad
size
PD
48
0.32
1.75
Watts
W/
C
Watts
Operating and Storage Temperature
Range
TJ, Tstg
55 to
175
C
Single Pulse DraintoSource Avalanche
Energy Starting TJ = 25
C
(VDD = 25 Vdc, VGS = 10 Vdc,
IL = 12 Apk, L = 1.0 mH, RG = 25
)
EAS
72
mJ
Thermal Resistance
Junction to Case
Junction to Ambient
Junction to Ambient, when mounted to
minimum recommended pad size
R
JC
R
JA
R
JA
3.13
100
71.4
C/W
Maximum Temperature for Soldering
Purposes, 1/8
from case for 10
seconds
TL
260
C
PIN ASSIGNMENT
1
Gate
3
Source
2
Drain
4
Drain
12 AMPERES
60 VOLTS
RDS(on) = 150 m
Device
Package
Shipping
ORDERING INFORMATION
MTD3055V
DPAK
75 Units/Rail
CASE 369A
DPAK
STYLE 2
http://onsemi.com
NChannel
D
S
G
MTD3055V1
DPAK
75 Units/Rail
MARKING
DIAGRAM
Y
= Year
WW
= Work Week
T
= MOSFET
YWW
T
3055V
MTD3055VT4
DPAK
2500 Tape & Reel
1
2
3
4
Preferred devices are recommended choices for future use
and best overall value.
MTD3055V
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2
ELECTRICAL CHARACTERISTICS
(TJ = 25
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250
Adc)
Temperature Coefficient (Positive)
V(BR)DSS
60
65
Vdc
mV/
C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150
C)
IDSS
10
100
Adc
GateBody Leakage Current (VGS =
20 Vdc, VDS = 0)
IGSS
100
nAdc
ON CHARACTERISTICS (Note 1.)
Gate Threshold Voltage
(VDS = VGS, ID = 250
Adc)
Temperature Coefficient (Negative)
VGS(th)
2.0
2.7
5.4
4.0
Vdc
mV/
C
Static DrainSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc)
RDS(on)
0.10
0.15
Ohm
DrainSource OnVoltage (VGS = 10 Vdc)
(ID = 12 Adc)
(ID = 6.0 Adc, TJ = 150
C)
VDS(on)
1.3
2.2
1.9
Vdc
Forward Transconductance (VDS = 7.0 Vdc, ID = 6.0 Adc)
gFS
4.0
5.0
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V
25 Vd
V
0 Vd
Ciss
410
500
pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
130
180
Reverse Transfer Capacitance
f = 1.0 MHz)
Crss
25
50
SWITCHING CHARACTERISTICS (Note 2.)
TurnOn Delay Time
td(on)
7.0
10
ns
Rise Time
(VDD = 30 Vdc, ID = 12 Adc,
VGS = 10 Vdc
tr
34
60
TurnOff Delay Time
VGS = 10 Vdc,
RG = 9.1
)
td(off)
17
30
Fall Time
RG 9.1
)
tf
18
50
Gate Charge
(S
Fi
8)
QT
12.2
17
nC
(See Figure 8)
(VDS = 48 Vdc, ID = 12 Adc,
Q1
3.2
(VDS 48 Vdc, ID 12 Adc,
VGS = 10 Vdc)
Q2
5.2
Q3
5.5
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage (Note 1.)
(IS = 12 Adc, VGS = 0 Vdc)
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150
C)
VSD
1.0
0.91
1.6
Vdc
Reverse Recovery Time
(S
Fi
15)
trr
56
ns
(See Figure 15)
(IS = 12 Adc VGS = 0 Vdc
ta
40
(IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
tb
16
Reverse Recovery Stored
Charge
dIS/dt = 100 A/
s)
QRR
0.128
C
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
from package to center of die)
LD
4.5
nH
Internal Source Inductance
(Measured from the source lead 0.25
from package to source bond pad)
LS
7.5
nH
1. Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
2. Switching characteristics are independent of operating junction temperature.
MTD3055V
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3
TYPICAL ELECTRICAL CHARACTERISTICS
0
1
2
3
4
5
0
8
16
24
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. OnRegion Characteristics
I D
, DRAIN CURRENT
(AMPS)
2
4
6
8
10
0
8
16
24
I D
, DRAIN CURRENT
(AMPS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0
8
12
16
20
24
0
0.1
0.2
0.3
R DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (OHMS)
0
4
8
16
20
24
0.08
0.09
0.11
0.13
0.15
ID, DRAIN CURRENT (AMPS)
Figure 3. OnResistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. OnResistance versus Drain Current
and Gate Voltage
0
20
30
40
50
60
1
10
100
Figure 5. OnResistance Variation with
Temperature
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 6. DrainToSource Leakage
Current versus Voltage
R DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (OHMS)
I DSS
, LEAKAGE (nA)
TJ = 25
C
VDS
10 V
TJ = - 55
C
25
C
100
C
-55
C
VGS = 10 V
9 V
8 V
7 V
6 V
5 V
4 V
4
12
20
3
5
7
9
4
12
20
TJ = 25
C
VGS = 10 V
25
C
4
0.05
0.15
0.25
VGS = 10 V
15 V
12
0.1
0.12
0.14
VGS = 0 V
TJ = 125
C
10
TJ = 100
C
R DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE
(NORMALIZED)
- 50
0.6
0.8
1.2
1.6
TJ, JUNCTION TEMPERATURE (
C)
- 25
0
25
50
75
100
125
150
VGS = 10 V
ID = 6 A
1.0
1.4
175
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4
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
10
5
0
10
25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE (pF)
Figure 7. Capacitance Variation
VGS
VDS
TJ = 25
C
VDS = 0 V
VGS = 0 V
1200
1000
800
600
400
200
0
Ciss
Coss
15
Crss
Ciss
Crss
20
5
MTD3055V
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5
VDS
, DRAIN-T
O-SOURCE VOL
T
AGE (VOL
TS)
V GS
, GA
TE-T
O-SOURCE VOL
T
AGE (VOL
TS)
DRAINTOSOURCE DIODE CHARACTERISTICS
0.5
0.6
0.7
0.8
0.9
1.0
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 8. GateToSource and DrainToSource
Voltage versus Total Charge
I S
, SOURCE CURRENT
(AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
1
10
100
t, TIME
(ns)
VDD = 30 V
ID = 12 A
VGS = 10 V
TJ = 25
C
tr
tf
td(off)
td(on)
VGS = 0 V
TJ = 25
C
Figure 10. Diode Forward Voltage versus Current
0
QT, TOTAL CHARGE (nC)
4
6
9
11
13
ID = 12 A
TJ = 25
C
VDS
0
2
6
10
12
1000
100
10
1
10
6
2
0
12
8
4
60
50
40
30
20
10
0
VGS
3
5
7
10
12
1
2
0.55
0.65
0.75
0.85
0.95
4
8
QT
8
Q2
Q1
Q3
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25
C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal
ResistanceGeneral Data and Its Use."
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10
s. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) TC)/(R
JC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
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