Semiconductor Components Industries, LLC, 2005
December, 2005 - Rev. 0
1
Publication Order Number:
NB4N11S/D
NB4N11S
3.3 V 1:2 AnyLevelTM Input
to LVDS Fanout Buffer /
Translator
The NB4N11S is a differential 1:2 Clock or Data Receiver and will
accept AnyLevel
TM
input signals: LVPECL, CML, LVCMOS,
LVTTL, or LVDS. These signals will be translated to LVDS and two
identical copies of Clock or Data will be distributed, operating up to
2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N11S is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock or Data
distribution applications.
The NB4N11S has a wide input common mode range from
GND + 50 mV to V
CC
- 50 mV. Combined with the 50
W internal
termination resistors at the inputs, the NB4N11S is ideal for
translating a variety of differential or single-ended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB4N11S is functionally equivalent to the EP11, LVEP11,
SG11 or 7L11M devices and is offered in a small 3 mm X 3 mm
16-QFN package. Application notes, models, and support
documentation are available at www.onsemi.com.
Features
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2
23-1
(V
INPP
= 400 mV; Input Signal DDJ = 14 ps)
VOL
T
AGE
(130 mV/div)
Device DDJ = 10 ps
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN-16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
16
NB4N
11S
ALYW
1
1
Q0
Q0
Q1
Q1
D
D
V
TD
V
TD
Figure 1. Logic Diagram
NB4N11S
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2
Figure 3. NB4N11S Pinout, 16-pin QFN
(Top View)
V
CC
NC
V
EE
V
EE
V
CC
V
TD
D
D
V
TD
Q0
Q0
Q1
Q1
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB4N11S
Exposed Pad (EP)
V
CC
V
CC
V
CC
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q0
LVDS Output
Non-inverted D output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
2
Q0
LVDS Output
Inverted D output. Typically loaded with 100
W
receiver termination resistor
across differential pair.
3
Q1
LVDS Output
Non-inverted D output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
4
Q1
LVDS Output
Inverted D output. Typically loaded with 100
W
receiver termination resistor
across differential pair.
5
V
CC
-
Positive Supply Voltage.
6
NC
No Connect.
7
V
EE
Negative Supply Voltage.
8
V
EE
Negative Supply Voltage.
9
V
TD
-
Internal 50
W
termination pin for D.
10
D
LVPECL, CML, LVDS,
LVCMOS, LVTTL
Inverted Differential Clock/Data Input (Note 1).
11
D
LVPECL, CML, LVDS,
LVCMOS, LVTTL
Non-inverted Differential Clock/Data Input (Note 1).
12
V
TD
-
Internal 50
W
termination pin for D.
13
V
CC
-
Positive Supply Voltage.
14
V
CC
-
Positive Supply Voltage.
15
V
CC
-
Positive Supply Voltage.
16
V
CC
-
Positive Supply Voltage.
EP
Exposed pad. The exposed pad (EP) on the package bottom must be
attached to a heat-sinking conduit. The exposed pad may only be
electrically connected to V
EE
.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self-oscillation.
NB4N11S
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3
Table 2. ATTRIBUTES
Characteristics
Value
Moisture Sensitivity (Note 2)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 1 kV
Transistor Count
225
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
CC
Positive Power Supply
GND = 0 V
3.8
V
V
IN
Positive Input
GND = 0 V
V
IN
V
CC
3.8
V
I
IN
Input Current Through R
T
(50
W
Resistor)
Static
Surge
35
70
mA
mA
I
OSC
Output Short Circuit Current
Line-to-Line (Q to Q)
Line-to-End (Q or Q to GND)
Q or Q to GND
Q to Q
Continuous
Continuous
12
24
mA
T
A
Operating Temperature Range
QFN-16
-40 to +85
C
T
stg
Storage Temperature Range
-65 to +150
C
q
JA
Thermal Resistance (Junction-to-Ambient) (Note 3)
0 lfpm
500 lfpm
QFN-16
QFN-16
41.6
35.2
C/W
C/W
q
JC
Thermal Resistance (Junction-to-Case)
1S2P (Note 3)
QFN-16
4.0
C/W
T
sol
Wave Solder
Pb
Pb-Free
<3 Sec @ 248
C
<3 Sec @ 260
C
265
265
C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
3. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB4N11S
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4
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= -40
C to +85
C
Symbol
Characteristic
Min
Typ
Max
Unit
I
CC
Power Supply Current (Note 8)
35
50
mA
DIFFERENTIAL INPUTS DRIVEN SINGLE-ENDED (Figures 11, 12, 16, and 18)
V
th
Input Threshold Reference Voltage Range (Note 7)
GND +100
V
CC
- 100
mV
V
IH
Single-ended Input HIGH Voltage
V
th
+ 100
V
CC
mV
V
IL
Single-ended Input LOW Voltage
GND
V
th
- 100
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8, 9, 10, 17, and 19)
V
IHD
Differential Input HIGH Voltage
100
V
CC
mV
V
ILD
Differential Input LOW Voltage
GND
V
CC
- 100
mV
V
CMR
Input Common Mode Range (Differential Configuration)
GND + 50
V
CC
- 50
mV
V
ID
Differential Input Voltage (V
IHD
- V
ILD
)
100
V
CC
mV
R
TIN
Internal Input Termination Resistor
40
50
60
W
LVDS OUTPUTS (Note 4)
V
OD
Differential Output Voltage
250
450
mV
D
V
OD
Change in Magnitude of V
OD
for Complimentary Output States (Note 9)
0
1
25
mV
V
OS
Offset Voltage (Figure 15)
1125
1375
mV
D
V
OS
Change in Magnitude of V
OS
for Complimentary Output States (Note 9)
0
1
25
mV
V
OH
Output HIGH Voltage (Note 5)
1425
1600
mV
V
OL
Output LOW Voltage (Note 6)
900
1075
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVDS outputs require 100
W
receiver termination resistor between differential pair. See Figure 14.
5. V
OH
max = V
OS
max +
V
OD
max.
6. V
OL
max = V
OS
min -
V
OD
max.
7. V
th
is applied to the complementary input when operating in single-ended mode.
8. Input termination pins open, D/D at the DC level within V
CMR
and output pins loaded with R
L
= 100
W
across differential.
9. Parameter guaranteed by design verification not tested in production.
NB4N11S
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5
Table 5. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND
= 0 V; (Note 10)
Symbol
Characteristic
-40
C
25
C
85
C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
V
OUTPP
Output Voltage Amplitude (@ V
INPPmin
) f
in
1.0 GHz
(Figure 4)
f
in
= 1.5 GHz
f
in
= 2.0 GHz
220
200
170
350
300
270
250
200
170
350
300
270
250
200
170
350
300
270
mV
f
DATA
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
t
PLH
,
t
PHL
Differential Input to Differential Output
Propagation Delay
270
370
470
270
370
470
270
370
470
ps
t
SKEW
Duty Cycle Skew (Note 11)
Within Device Skew (Note 16)
Device-to-Device Skew (Note 15)
8
5
30
45
25
100
8
5
30
45
25
100
8
5
30
45
25
100
ps
t
JITTER
RMS Random Clock Jitter (Note 13)
f
in
= 1.0 GHz
f
in
= 1.5 GHz
Deterministic Jitter (Note 14)
f
DATA
= 622 Mb/s
f
DATA
= 1.5 Gb/s
f
DATA
= 2.488 Gb/s
0.5
0.5
6
7
10
1
1
20
20
0.5
0.5
6
7
10
1
1
20
20
0.5
0.5
6
7
10
1
1
20
20
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 12)
100
V
CC
-
GND
100
V
CC
-
GND
100
V
CC
-
GND
mV
t
r
t
f
Output Rise/Fall Times @ 250 MHz
Q, Q
(20% - 80%)
70
120
170
70
120
170
70
120
170
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing V
INPPmin
with 50% duty cycle clock source and V
CC
- 1400 mV offset. All loading with an external R
L
= 100
W
across
"D" and "D" of the receiver. Input edge rates 150 ps (20%-80%).
11. See Figure 13 differential measurement of t
skew
= |t
PLH
- t
PHL
| for a nominal 50% differential clock input waveform @ 250 MHz.
12. Input voltage swing is a single-ended measurement operating in differential mode.
13. RMS jitter with 50% Duty Cycle clock signal at 750 MHz.
14. Deterministic jitter with input NRZ data at PRBS 2
23
-1 and K28.5.
15. Skew is measured between outputs under identical transition @ 250 MHz.
16. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) and Temperature (@ V
CC
= 3.3 V)
OUTPUT
VOL
T
AGE
AMPLITUDE
(mV)
0
50
100
150
200
250
300
350
400
0.5
1
1.5
2
2.5
3
0
85
C
-40
C
25
C
NB4N11S
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6
TIME (58 ps/div)
Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 2
23-1
and OC48 mask
(V
INPP
= 100 mV; Input Signal DDJ = 14 ps)
VOL
T
AGE
(63.23 mV/div)
Device DDJ = 10 ps
R
C
R
C
1.25 k
W
1.25 k
W
1.25 k
W
1.25 k
W
50
W
50
W
Dx
V
TDx
V
TDx
D
x
Figure 6. Input Structure
I
NB4N11S
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7
GND
V
CC
GND
LVPECL
Driver
D
50
W
*
Z
o
= 50
W
Z
o
= 50
W
50
W
*
D
NB4N11S
V
CC
V
TD
GND
V
CC
GND
CML
Driver
50
W
*
Z
o
= 50
W
Z
o
= 50
W
50
W
*
NB4N11S
V
CC
V
TD
= V
TD
= V
CC
Figure 7. LVPECL Interface
Figure 8. LVDS Interface
V
TD
= V
TD
= V
CC
- 2.0 V
Figure 9. Standard 50
W
Load CML Interface
GND
V
CC
GND
LVDS
Driver
50
W
*
Z
o
= 50
W
Z
o
= 50
W
50
W
*
NB4N11S
V
CC
V
TD
= V
TD
GND
V
CC
GND
HSTL
Driver
50
W
*
Z
o
= 50
W
Z
o
= 50
W
50
W
*
NB4N11S
V
CC
V
TD
= V
TD
= GND or V
DD
/2
Depending on Driver.
Figure 10. HSTL Interface
GND
V
CC
GND
LVCMOS
Driver
50
W
*
Z
o
= 50
W
50
W
*
NB4N11S
V
CC
V
TD
= V
TD
= OPEN
D = GND
Figure 11. LVCMOS Interface
GND
V
CC
GND
LVTTL
Driver
50
W
*
Z
o
= 50
W
50
W
*
NB4N11S
V
CC
V
TD
= OPEN
D = GND
Figure 12. LVTTL Interface
V
TD
D
D
V
TD
V
TD
D
V
TD
V
TD
V
CC
D
D
V
TD
V
TD
D
D
V
TD
V
TD
D
GND
D
V
TD
V
TD
D
GND
*R
TIN
, Internal Input Termination Resistor.
NB4N11S
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8
Figure 13. AC Reference Measurement
D
D
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(D) - V
IL
(D)
V
OUTPP
= V
OH
(Q) - V
OL
(Q)
Figure 14. Typical LVDS Termination for Output Driver and Device Evaluation
Driver
Device
Receiver
Device
Q
D
Q
D
LVDS
100
W
LVDS
Z
o
= 50
W
Z
o
= 50
W
V
OL
Q
N
V
OH
Q
N
V
OS
V
OD
Figure 15. LVDS Output
Figure 16. Differential Input Driven
Single-Ended
D
Figure 17. Differential Inputs Driven
Differentially
D
V
th
V
th
D
D
V
IH
V
IL
V
IHmax
V
ILmax
V
IHmin
V
ILmin
V
CC
V
thmax
V
thmin
GND
V
th
Figure 18. V
th
Diagram
D
D
V
IL
V
IH(MAX)
V
IH
V
IL
V
IH
V
IL(MIN)
V
CMR
GND
Figure 19. V
CMR
Diagram
V
INPP
= V
IHD
- V
ILD
V
CC
NB4N11S
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9
ORDERING INFORMATION
Device
Package
Shipping
NB4N11SMNG
QFN-16, 3 X 3 mm
(Pb-Free)
123 Units / Rail
NB4N11SMNR2G
QFN-16, 3 X 3 mm
(Pb-Free)
3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NB4N11S
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10
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G-01
ISSUE B
16X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
1
4
5
8
12
9
16
13
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. L
max
CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
B
A
0.15 C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
LOCATION
0.10 C
0.08 C
(A3)
C
16 X
e
16X
NOTE 5
0.10 C
0.05 C
A B
NOTE 3
K
16X
DIM
MIN
MAX
MILLIMETERS
A
0.80
1.00
A1
0.00
0.05
A3
0.20 REF
b
0.18
0.30
D
3.00 BSC
D2
1.65
1.85
E
3.00 BSC
E2
1.65
1.85
e
0.50 BSC
K
0.20
---
L
0.30
0.50
EXPOSED PAD
mm
inches
SCALE 10:1
0.50
0.02
0.575
0.022
1.50
0.059
3.25
0.128
0.30
0.012
3.25
0.128
0.30
0.012
EXPOSED PAD
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
NB4N11S/D
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