Publication Order Number:

NBLVEP16VR/D

Semiconductor Components Industries, LLC, 2003

December, 2003 - Rev. 2

NBLVEP16VR

2.5V/3.3V/5V ECL
Differential Receiver/Driver
with Oscillator Gain Stage
and Enabled High Gain
Outputs

The NBLVEP16VR is an ECL/LVPECL oscillator gain stage with

high-gain output buffers, selectable output enable and a feedback
buffer. The NBLVEP16VR is a solution for crystal oscillators and
SAW-based voltage-controlled oscillators.

Q and Q Outputs have Selectable 4 mA or 8 mA, Self Bias Current

Sources

QHG and QHG have a Selectable 10 mA, Self Bias Current Sources

Synchronous Output Enable of the High-Gain Outputs with

Selectable Disabled State

Selectable LVCMOS/LVTTL or LVPECL Level Input of the Output

Enable Pin

Maximum Frequency > 2.5 GHz Typical

(LV)PECL Mode Operating Range: V

= 2.375 V to 5.5 V with

= 0 V

NECL Mode Operating Range: V

= 0 V with

= -2.375 V to -5.5 V

Temperature Compensated Inputs and Outputs

Excellent Clock Input Sensitivity

Output Supports Current Source/Sink Capability up to a

Robust 1.5 mA

Q
Q

D
D

OD_MODE

Figure 1. Logic Diagram

CS_SEL

QHG

EEP

EN_SEL

Q
Q

LVCMOS/LVTTL

Threshold

470

10 mA ea. (opt.)

4 mA ea.

4 mA ea. (opt.)

BB_ADJ

LEN

LATCH

Device

Package

Shipping

ORDERING INFORMATION

NBLVEP16VRMN

QFN-16

123 / Rail

NBLVEP16VRMNR2

QFN-16

3000/ Tape &

Reel

QFN-16

MN SUFFIX

CASE 485G

MARKING DIAGRAM

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XXXX
XXXX

ALYW

XXXX = Device Code
A

= Assembly Location

= Wafer Lot

= Year

= Work Week

Bottom View

NBWLVEP16VR

Wafer

Refer to

Note 1.

1. Contact Sales Representative.

For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

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Q
Q

D
D

OD_MODE

Figure 2. Logic Diagram

CS_SEL

QHG

EEP

EN_SEL

Q
Q

LVCMOS/LVTTL

Threshold

470

10 mA ea. (opt.)

4 mA ea.

4 mA ea. (opt.)

BB_ADJ

LEN

LATCH

Table 1. Q AND Q INTERNAL CURRENT SOURCE
SELECTOR

CS_SEL

See Figure

OPEN

4 mA Typical

13, 13

8 mA Typical

10, 13

0 mA

4 mA Typical

13, 13

Table 2. QHG AND QHG INTERNAL CURRENT
SOURCE SELECTOR

EEP

QHG

See Figure

OPEN

0 mA

8, 11

10 mA Typical

9, 12

Table 3. OUTPUT ENABLE AND OUTPUT DISABLED STATE TRUTH TABLE

EN_SEL

OD-MODE*

EN*

Q and Q

QHG

or OPEN

Low or OPEN

LVPECL Low, V

or OPEN

Data

or OPEN

Low or OPEN

LVPECL High or V

Data

Low

High

Low or OPEN

LVCMOS Low, V

, or OPEN

Data

Low

High

Low or OPEN

LVCMOS High or V

Data

or OPEN

High

LVPECL Low, V

or OPEN

Data

or OPEN

High

LVPECL High or V

Data

High

Low

High

LVCMOS Low, V

, or OPEN

Data

High

Low

High

LVCMOS High or V

Data

*Pins will default LOW when left open.
Pin will default HIGH when left open.

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Figure 3. Pinout Diagram

(Top View)

OD_MODE

CS_SEL

QHG

EEP

EN_SEL

BB_ADJ

NBLVEP16VR

Exposed Pad

(EP)

Figure 4. Die Map

OD_MODE

CS_SEL

QHG

EN_SEL

BB_ADJ

NBLVEP16VR

Die: 1.16 x 1.19 mm

EEP

(x)

(y)

Bond Pad: 84

m Diameter

Table 4. PIN DESCRIPTION

Pin No

Name

I/O

Description

OD_MODE*

LVCMOS/LVTTL Input (See Table 3)

Selectable Mode of Output Disabled Level

ECL / LVPECL Input

Clock / Data Input

ECL / LVPECL Input

Inverted Clock / Data Input

Reference Voltage Output

EN*

ECL / LVPECL or LVCMOS/LVTTL Input
(see Table 3)

Output Enable Synchronous with D and D

BB_ADJ

Adjust Standard V

Levels Upward When Tied to V

for

2.5 V Power Supply. Open for 3.3 V and 5 V Power Supply.

Negative Power Supply

EEP

Open or Tied to V

(See Table 1) Optional 10mA Current

Source For QHG and QHG

EN_SEL

LVCMOS / LVTTL Input (See Table 3)

Input LVEL Selector Pin for EN

QHG

ECL / LVPECL Output

Inverted High-Gain Output, Gain > 200

QHG

ECL / LVPECL Output

High-Gain Output, Gain > 200

CS_SEL

Selects Q and Q Current Source Magnitude (see Table 1),
Open or Tied to V

or V

Positive Power Supply

No Connect

ECL / LVPECL Output

ECL/LVPECL Output for Feedback Loop

ECL / LVPECL Output

Inverted ECL/LVPECL Output for Feedback Loop

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Supply (OPT)

Exposed Pad on Package Bottom Should Only Be Con-
nected to V

or Left Open

*Pins will default LOW when left open.
Pin will default HIGH when left open.

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APPLICATIONS INFORMATION

The NBLVEP16VR is an ECL/LVPECL oscillator gain

stage with high-gain output buffers, selectable output
enable and a feedback buffer. The NBLVEP16VR is a
solution for crystal oscillators and SAW-based
voltage-controlled oscillators. Design versatility is
enhanced with EN, a synchronous output enable pin to
eliminate runt pulses; EN_SEL, an input state selector pin
offering LVCMOS/LVTTL or ECL/LVPECL level control
of EN; and OD_MODE, an output disable mode state pin
which selects the polarity of the high-gain output's disabled
state.

The NBLVEP16VR Q and Q outputs are ideal for

feedback applications common in crystal oscillator gain
blocks. They each have a selectable on-chip pull-down
current source. External resistors may be used to increase the
pull-down current to a maximum of 25 mA. The QHG and
QHG outputs each have an optional on-chip pull-down
current source of 10 mA. When V

EEP

is left open, the 10 mA

output current sources are disabled and the QHG and QHG
outputs operate as standard ECL/LVPECL. When V

EEP

connected to V

, the 10 mA current sources are activated.

The QHG and QHG pull-down current can be decreased by
using a resistor connect from V

EEP

to V

. See current

source truth table for functions and options.

The output enable input pin, EN, is synchronized with the

D and D data input signals in a way that furnishes glitchless
gating of the QHG and QHG outputs and allows continuous
oscillator operation. For applications that require output
enable control, the NBLVEP16VR provides expanded
output enable selectability. The logic level of the input state
selector pin, EN_SEL, will determine whether the EN pin
accepts ECL/LVPECL or LVCMOS/LVTTL logic levels.

The output disable mode state pin, OD_MODE, adds

functional flexibility by giving the designer a choice of the
QHG outputs' polarity when these high-gain outputs are
disabled. For example, with OD_MODE LOW and
EN LOW (LVPECL), the input is passed to the outputs and
the data output equals the data input. If the D input is LOW
when the EN goes HIGH, the next data transition to a HIGH
is ignored and QHG remains LOW and QHG remains
HIGH. The next positive transition of the data input is not
passed on to the QHG outputs under these conditions. The
QHG and QHG outputs remain in their disabled state as long
as the EN input is held HIGH. The EN input has no influence
on the Q or Q outputs and the data inputs are passed on to
these outputs whether EN is HIGH or LOW. When the data
input is HIGH and EN goes HIGH, it will force QHG LOW
and QHG HIGH on the next negative transition of the D
input. This configuration is ideal for crystal oscillator
applications where the oscillator can be free-running and
QHG/QHG gate on and off synchronously without adding
extra counts to the output. See truth table and timing diagram
for detailed ENable functions and options.

The NBLVEP16VR provides a V

and internal 470

bias resistors from D to V

and D to V

for ac coupled

single-ended or differential input signal(s). The V

BB_ADJ

pin is used for 2.5 V single-ended operation when it is
connected to V

. The V

output current source/sink

capability can support a robust 1.5 mA.

For single-ended input conditions, the unused differential

input is internally connected to V

as a switching reference

voltage. Decouple V

and V

with a 0.01

mF capacitor.

This internal V

will rebias AC coupled input(s). Inputs D

or D must be signal driven or auto oscillation may result.

OD_MODE

QHG

(PECL)

(CMOS)

EN_SEL HIGH (OPEN)

EN_SEL LOW

(SHORTED TO V

)

Figure 5. Timing Diagram

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ATTRIBUTES

Characteristics

Value

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 150 V

> 1 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

Transistor Count

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Rating

Unit

LVPECL Mode Power Supply

= 0 V

NECL Mode Power Supply

= 0 V

-6

LVPECL Mode Input Voltage

NECL Mode Input Voltage

= 0 V

-6

Current Sink/Source

1.5

Input Current (V

- V

)

470

D, D

out

Output Current

Continuous

Surge

100

Operating Temperature Range

-40 to +85

stg

Storage Temperature Range

-65 to +150

Thermal Resistance (Junction-to-Ambient)

0 LFPM

500 LFPM

C/W

Thermal Resistance (Junction-to-Case)

Standard Board

C/W

Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.

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DC CHARACTERISTICS, LVPECL

= 2.5 V, V

= 0 V (Note 2, 6)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current (Note 3)

Output HIGH Voltage (Note 4)

1340

1670

1340

1670

1340

1670

Output LOW Voltage (Note 4)

620

950

620

950

620

950

Input High Voltage (Single-Ended)
(D, D, EN) (Notes 5, 6)

1655

2000

1655

2000

1655

2000

Input Low Voltage (Single-Ended)
(D, D, EN) (Notes 5, 6)

1050

1395

1050

1395

1050

1395

Output Voltage Reference (Note 6)

1420

1525

1630

1420

1525

1630

1420

1525

1630

IHCMR

Input High Voltage Common Mode Range
(Differential Configuration)

1.2

2.5

1.2

2.5

1.2

2.5

Input HIGH Current (Note 5)

150

Input LOW Current (Note 5)

0.5

NOTE:

LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is
maintained.

2. Input and output parameters vary 1:1 with V

3. V

EEP

and CS_SEL open.

4. QHG/QHG outputs loaded with 50

to V

- 2.0 V (V

EEP

= OPEN) Figure 11 or with optional current source (V

EEP

= V

) Figure 12.

Q/Q outputs loaded with 8 mA current source (CS_SEL = V

5. EN_SEL Open.
6. V

BB_ADJ

tied to V

for 2.5 V single-ended input operation.

DC CHARACTERISTICS, LVPECL

= 3.3 V, V

= 0 V (Note 7)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current (Note 8)

Output High Voltage (Note 9)

2140

2470

2140

2470

2140

2470

Output Low Voltage (Note 9)

1420

1750

1420

1750

1420

1750

Input High Voltage (Single-Ended)
(D, D, EN) (Note 10)

2075

2420

2075

2420

2075

2420

Input Low Voltage (Single-Ended)
(D, D, EN) (Note 10)

1355

1675

1355

1675

1355

1675

Output Voltage Reference

1790

1900

2030

1790

1900

2030

1790

1900

2030

IHCMR

Input High Voltage Common Mode Range
(Differential Configuration)

1.2

3.3

1.2

3.3

1.2

3.3

Input HIGH Current (Note 10)

150

Input LOW Current (Note 10)

0.5

NOTE:

7. Input and output parameters vary 1:1 with V

8. V

EEP

and CS_SEL open.

9. QHG/QHG outputs loaded with 50

to V

- 2.0 V (V

EEP

= OPEN) Figure 11 or with optional current source (V

EEP

= V

) Figure 12.

Q/Q outputs loaded with 8 mA current source (CS_SEL = V

10. EN_SEL Open.

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DC CHARACTERISTICS, PECL

= 5.0 V, V

= 0 V (Note 11)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current (Note 12)

Output High Voltage (Note 13)

3840

4170

3840

4170

3840

4170

Output Low Voltage (Note 13)

3120

3450

3120

3450

3120

3450

Input High Voltage (Single-Ended)
(D, D, EN) (Note 14)

3775

4120

3775

4120

3775

4120

Input Low Voltage (Single-Ended)
(D, D, EN) (Note 14)

3055

3375

3055

3375

3055

3375

Output Voltage Reference

3490

3600

3730

3490

3600

3730

3490

3600

3730

IHCMR

Input High Voltage Common Mode Range
(Differential Configuration)

2.0

5.0

2.0

5.0

2.0

5.0

Input HIGH Current (Note 14)

150

Input LOW Current (Note 14)

0.5

NOTE:

11. Input and output parameters vary 1:1 with V

12. V

EEP

and CS_SEL open.

13. QHG/QHG outputs loaded with 50

to V

- 2.0 V (V

EEP

= OPEN) Figure 11 or with optional current source (V

EEP

= V

) Figure 12.

Q/Q outputs loaded with 8 mA current source (CS_SEL = V

14. EN_SEL Open.

DC CHARACTERISTICS, NECL

= 0 V, V

= -5.5V to -2.375 V (Note 15)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current
(Note 16)

Output High Voltage (Note 17)

-1160

-830

-1160

-830

-1160

-830

Output Low Voltage (Note 17)

-1880

-1550

-1880

-1550

-1880

-1550

Input High Voltage (Single-Ended)
(D, D, EN) (Notes 18, 19)
-3.3 V

BB_ADJ

= OPEN

-2.5 V

BB_ADJ

= V

-1225

-845

-880
-500

-1225

-845

-880
-500

-1225

-845

-880
-500

Input Low Voltage (Single-Ended)
(D, D, EN) (Notes 18, 19)
-3.3 V

BB_ADJ

= OPEN

-2.5 V

BB_ADJ

= V

-1945
-1450

-1625

-1105

-1945
-1450

-1625

-1105

-1945
-1450

-1625

-1105

Output Voltage Reference
-3.3 V or -5.2 V

BB_ADJ

= OPEN

-2.5 V (Note 19)

BB_ADJ

= V

-1510
-1080

-1400

-975

-1270

-870

-1510
-1080

-1400

-975

-1270

-870

-1510
-1080

-1400

-975

-1270

-870

IHCMR

Input High Voltage Common Mode
Range (Differential Configuration)
V

-5 V

+1.2

+2.0

+1.2

+2.0

+1.2

+2.0

Input HIGH Current (Note 18)

150

Input LOW Current (Note 18)

0.5

NOTE:

15. Input and output parameters vary 1:1 with V

16. V

EEP

and CS_SEL open.

17. QHG/QHG outputs loaded with 50

to V

- 2.0 V (V

EEP

= OPEN) Figure 11 or with optional current source (V

EEP

= V

) Figure 12.

Q/Q outputs loaded with 8 mA current source (CS_SEL = V

18. EN_SEL Open.
19. V

BB_ADJ

tied to V

for -2.5 V single-ended operation.

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(LVCMOS/LVTTL DC CHARACTERISTICS

= 2.375 V or 5.0 V, V

= 0 V or V

= 0 V, V

= -2.375 V to -5.5 V (Note 20)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Input High Voltage

+2.0

2.0

+2.0

Input Low Voltage

+0.8

Input HIGH Current

-150

150

-150

150

-150

150

Input LOW Current

-150

150

-150

150

-150

150

20. EN_SEL = LOW When EN is Used as a LVCMOS/LVTTL Input.

AC CHARACTERISTICS

= 2.375 V to 5.5 V; V

= 0 V or V

= 0 V V

= -2.375 V to -5.5 V (Note 21)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

OUTPP

Differential Output (QHG)

out

< 1 GHz

Voltage (Peak-to-Peak)

out

< 2 GHz

out

< 2.5 GHz

500
260
210

660
500
400

500
310
210

700
500
380

500
280
190

700
450
330

mV
mV

PLH

PHL

Propagation Delay (Differential)
Figure 10

D to Q (CS_SEL = OPEN)

Figure 10

D to Q (CS_SEL = V

)

Figure 8

D to QHG (V

EEP

Open)

Figure 9

D to QHG (V

EEP

= V

)

215
155
315
320

290
270
390
400

385
395
475
490

215
165
335
335

300
280
410
415

385
405
495
505

230
205
360
360

315
300
440
450

400
445
520
530

Set-Up Time

EN to D

0.5

Hold Time

EN to D

1.0

JITTER

Random Clock Jitter (RMS)

0.5

SKEW

Duty Cycle Skew (Note 23)

INPP

Differential Input Voltage

D to QHG

(Peak-to-Peak) (Note 22)

D to Q

Single-Ended Configuration

D to QHG

25
50
50

800
800

1200
1200

25
50
50

800
800

1200
1200

25
50
50

800
800

1200
1200

mV
mV
mV

Output Rise/Fall Times (20% - 80%)

Q, Q (CS_SEL = V

or OPEN)

QHG, QHG (V

EEP

= V

or OPEN)

70
90

120
150

300
210

70
90

120
150

300
210

70
90

120
150

300
210

Output Duty Cycle (Note 24) (QHG)

21. QHG/QHG and Q/Q outputs loaded with AC coupled 50

loads. V

EEP

and CS_SEL connected to V

22. V

INPP

is the minimum differential Peak-to-Peak input swing for which AC parameters are guaranteed.

23. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point

of the outputs, (t

pLH

pHL

24. Assumes 50% Input Duty Cycle, see Figures 11 or 12.

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Figure 8. Typical Termination for Output Driver

EEP

Open (See Application Note AND8020 - Termination of ECL Logic Devices.)

Figure 9. QHG/QHG Output Loading and Termination, V

EEP

= V

Driver

Receiver

Figure 10. Q/Q Output Loading and Termination, CS_SEL Open or Tied to V

or V

Driver

Receiver

QHG

CS_SEL (Open or Tied to V

)

*R = 2 Z

= 100

for 50

Transmission

Lines

EEP

*R = 2 Z

= 100

for 50

Transmission Lines

Driver

Receiver

QHG

EEP

(OPEN)

= 50

= V

- 2.0 V

= 50

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D
D

OD_MODE

CS_SEL

QHG

EEP

EN_SEL

Q
Q

LVCMOS/LVTTL

Threshold

470

10 mA ea.

4.0 mA ea.

Figure 14. Typical Application

BB_ADJ

LEN

LATCH

The VCXO, or voltage controlled crystal oscillator, is an

oscillator where the output frequency is controlled by the
crystal and an external control voltage. The VCXO can have
the output frequency change with a change in voltage at a
control pin of the oscillator. Most, if not all, VCXO's use
varactor diodes to vary the frequency. A varactor diode is a
semiconductor device that behaves as a variable capacitor

when a voltage is applied to it. Thus, when a change in the
control voltage is applied to the control pin of the oscillator,
it causes a change in the capacitance seen by the crystal
internal to the oscillator. These changes in the circuit load
capacitance cause changes in the oscillator output frequency
due to crystal loading.

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PACKAGE DIMENSIONS

QFN-16

CASE 485G-01

ISSUE A

-T-

-X-

NOTE 3

SEATING

PLANE

-Y-

0.25 (0.010) T

0.08 (0.003) T

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

3.00 BSC

0.118 BSC

3.00 BSC

0.118 BSC

0.80

1.00

0.031

0.039

0.23

0.28

0.009

0.011

0.50 BSC

0.020 BSC

0.875

0.925

0.034

0.036

0.20 REF

0.008 REF

0.00

0.05

0.000

0.002

0.35

0.45

0.014

0.018

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

1.75

1.85

0.069

0.073

1.75

1.85

0.069

0.073

1.50 BSC

0.059 BSC

1.50 BSC

0.059 BSC

0.875

0.925

0.034

0.036

0.60

0.80

0.024

0.031

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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