Semiconductor Components Industries, LLC, 2000
May, 2000 Rev. 0
1
Publication Order Number:
NCP1232/D
NCP1232
Microprocessor Monitor
The NCP1232 is a fullyintegrated processor supervisor. It provides
three important functions to safeguard processor functionality:
precision power on/off reset control, watchdog timer and external
reset override.
On powerup, the NCP1232 holds the processor in the reset state for
a minimum of 250 msec after VCC is within tolerance to ensure a
stable system startup.
Microprocessor functionality is monitored by the onboard
watchdog circuit. The microprocessor must provide a periodic
lowgoing signal on the ST input. Should the processor fail to supply
this signal within the selected timeout period (150 msec, 600 msec or
1200 msec), an outofcontrol processor is indicated and the
NCP1232 issues a processor reset as a result.
The outputs of the NCP1232 are immediately driven active when
the PB input is brought low by an external pushbutton switch or other
electronic signal. When connected to a pushbutton switch, the
NCP1232 provides contact debounce.
The NCP1232 is packaged in a spacesaving 8pin plastic SOIC
package and requires no external components.
Features
Precision Voltage Monitor
(Adjustable +4.5 V or +4.75 V)
Reset Pulse Width (250 msec Min)
No External Components
Adjustable Watchdog Timer
(150 msec, 600 msec or 1.2 sec)
Debounced Manual Reset Input for External Override
Applications
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical
P Power Monitoring
YY, Y
= Year
WW
= Work Week
X
= Assembly ID Code
Z
= Subcontractor ID Code
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SO8
D SUFFIX
CASE 751
1
8
Device
Package
Shipping
ORDERING INFORMATION
NCP1232DR2
SO8
2500 Tape & Reel
NCP
1232
YWWXZ
1
8
MARKING
DIAGRAM
ST
RST
RST
GND
4
PB RST
1
2
3
8
7
6
5
(Top View)
PIN CONNECTIONS
8Pin SOIC
TD
TOL
VCC
NCP1232D
NCP1232
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2
FUNCTIONAL BLOCK DIAGRAM
VDCC
5%/10%
TOLERANCE
SELECT
DEBOUNCE
WATCHDOG
TIMEBASE
SELECT
WATCHDOG
TIMER
RESET
GENERATOR
TOL
PB RST
TD
RST
RST
ST
GND
NCP1232
REF
PIN DESCRIPTION
Pin No.
(8Pin SOIC)
Symbol
Description
1
PB RST
Pushbutton Reset Input. A debounced activelow input that ignores pulses less than 1 msec in
duration and is guaranteed to recognize inputs of 20 msec or greater.
2
TD
Time Delay Set. The watchdog timeout select input (tTD = 150 msec for
TD = 0 V, tTD = 600 msec for TD = open, tTD = 1.2 sec for TD = VCC.)
3
TOL
Tolerance Input. Connect to GND for 5% tolerance or to VCC for 10% tolerance.
4
GND
Ground.
5
RST
Reset Output (Active High) goes active:
1. If VCC falls below the selected reset voltage threshold
2. If PB RST is forced low
3. If ST is not strobed within the minimum timeout period
4. During powerup
6
RST
Reset Output (Active Low, Open Drain) see RST.
7
ST
Strobe Input. Input for watchdog timer.
8
VCC
The +5 V Power Supply Input.
NCP1232
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3
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin (with respect to GND) 0.3 V to +5.8 V
Rating
Value
Unit
Operating Temperature Range
40 to +85
C
Storage Temperature Range, Tstg
65 to +150
C
Lead Temperature (Soldering, 10 sec)
+300
C
*Stresses beyond those listed under "Absolute Maximum Ratings'' may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(TA = TMIN to TMAX; VCC = +4.5 V to 5.5 V, unless otherwise specified.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Voltage
VCC
4.5
5.0
5.5
V
ST and PB RST Input High Level
VIH
Note 1.
2.0
VCC +0.3
V
ST and PB RST Input Low Level
VIL
0.3
+0.8
V
Input Leakage ST, TOL
IL
1.0
+1.0
A
Output Current RST
IOH
VOH = 2.4 V
1.0
12
mA
Current RST, RST
IOL
VOL = 0.4 V
2.0
10
mA
Operating Current
ICC
Note 2.
50
200
A
VCC 5% Trip Point (Note 3.)
VCCTP
TOL = GND
4.50
4.62
4.74
V
VCC 10% Trip Point (Note 3.)
VCCTP
TOL = VCC
4.25
4.37
4.49
V
CAPACITANCE (Note 4.)
(TA = +25
C)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Capacitance ST, TOL
CIN
5.0
pF
Output Capacitance RST, RST
COUT
7.0
pF
AC ELECTRICAL CHARACTERISTICS
(TA = TMIN to TMAX; VCC = +5.0 V to
"
10%, unless otherwise specified.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
PB RST (Note 5.)
tPB
Figure 3
20
msec
PB RST Delay
tPBD
Figure 3
1.0
4.0
20
msec
Reset Active Time
tRST
250
610
1000
msec
ST Pulse Width
tST
Figure 4
20
nsec
ST Timeout Period
tTD
Figure 4
TD Pin = 0 V
TD Pin = Open
TD Pin = VCC
62.5
250
500
150
600
1200
250
1000
2000
msec
VCC Fall Time (Note 4.)
tF
Figure 5
10
sec
VCC Rise Time (Note 4.)
tR
Figure 6
0
sec
VCC Detect to RST High and RST Low
tRPD
Figure 7, VCC Falling
100
nsec
VCC Detect to RST High and RST Open
(Note 6.)
tRPU
Figure 8, VCC Rising
250
610
1000
msec
1. PB RST is internally pulled up to VCC with an internal impedance of typically 40 k
.
2. Measured with outputs open.
3. All voltages references to GND.
4. Guaranteed by design.
5. PB RST must be held low for a minimum of 20 msec to guarantee a reset.
6. tR = 5
sec.
NCP1232
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4
Power Monitor
The NCP1232 detects outoftolerance power supply
conditions and warns a processorbased system of an
impending power failure. When VCC is detected as below
the preset level defined by TOL, the VCC comparator
outputs the signals RST and RST. If TOL is connected to
ground, the RST and RST signals become active as VCC falls
below 4.75 volts. If TOL is connected to VCC, the RST and
RST become active as VCC falls below 4.5 volts. Because
the processing is stopped at the last possible moment of valid
VCC, the RST and RST are excellent control signals for a
P.
The reset outputs will remain in their active states until VCC
has been continuously intolerance for a minimum of 250
msec allowing the power supply and
P to stabilize before
RST is released.
Pushbutton Reset Input
The debounced manual reset input (PB RST) manually
forces the reset outputs into their active states. Once PB RST
has been low for a time, tPBD, the pushbutton delay time,
the reset outputs go active. The reset outputs remain in their
active states for a minimum of 250 msec after PB RST rises
above VIH (Figure 3).
A mechanical pushbutton or active logic signal can drive
the PB RST input. The debounced input ignores input pulses
less than 1 msec and is guaranteed to recognize pulses of
20 msec or greater. No external pullup resistor is required
because the PB RST input has an internal pullup to VCC of
approximately 100
A.
Watchdog Timer
When the ST input is not stimulated for a preset time
period, the watchdog timer function forces RST and RST
signals to the active state. The preset time period is
determined by the TD inputs to be 150 msec with TD
connected to ground, 600 msec with TD open, or 1200 msec
with TD connected to VCC, typical. The watchdog timer
starts timing out from the set time period as soon as RST and
RST are inactive. If a hightolow transition occurs on the
ST input pin prior to timeout, the watchdog timer is reset
and begins to timeout again. If the watchdog timer is
allowed to timeout, then the RST and RST signals are
driven to the active state for 250 msec minimum (Figure 2).
The software routine that strobes ST is critical. The code
must be in a section of software that is executed regularly so
the time between toggles is less than the watchdog timeout
period. One common technique controls the
P I/O line
from two sections of the program. The software might set the
I/O line high while operating in the foreground mode and set
it low while in the background or interrupt mode. If both
modes do not execute correctly, the watchdog timer issues
reset pulses.
Supply Monitor Noise Sensitivity
The NCP1232 is optimized for fast response to
negativegoing changes in VDD. Systems with an inordinate
amount of electrical noise on VDD (such as systems using
relays), may require a 0.01
F or 0.1
F bypass capacitor to
reduce detection sensitivity. This capacitor should be
installed as close to the NCP1232 as possible to keep the
capacitor lead length short.
RESET
VCC
TOL
PB RST
TD
RST
GND
NCP1232
ST
+5 V
I/O
MICRO
PROCESSOR
Figure 1. Pushbutton Reset
RESET
VCC
TOL
RST
TD
GND
NCP1232
ST
+5 V
MICRO
PROCESSOR
I/O
3TERMINAL
REGULATOR
0.1
F
10 K
+5 V
Figure 2. Watchdog Timer
NCP1232
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5
tPBD
tPB
RST
PB RST
RST
VIH
VIL
tRST
Figure 3. Pushbutton Reset. The debounced PB RST
input ignores input pulses less than 1 msec and is
guaranteed to recognized pulses of 20 msec or greater
Figure 4. Strobe Input
ST
tTD
tST
NOTE: tTD is the maximum elapsed time between ST hightolow
transistions (ST is activated by falling edges only) which will
keep the watchdog timer from forcing the reset outputs active
for a time of tRST. tTD is a function of the voltage at the TD pin,
as tabulated below.
CONDITION
MIN
TYP
TD PIN = 0 V
62.5 msec
150 msec
250 msec
TD PIN = OPEN
250 msec
600 msec
1000 msec
TD PIN = VCC
500 msec
1200 msec
2000 msec
MAX
TD
t
PUSHBUTTON RESET
NCP1232
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6
RST
RST
VCC
4.6 V (5% TRIP POINT)
4.5 V (10% TRIP POINT)
VCC = 5 V
+4.5 V (5% TRIP POINT)
+4.25 V (10% TRIP POINT)
tRPD
VCC, SLEW RATE = 1.66mV/
sec (0.5 V/300
sec)
RST
RST
tRPU
VOH
VOL
VOH
VOL
Figure 5. PowerDown Slew Rate
VCC
+4.75 V
+4.25 V
tF
Figure 6. PowerDown Slew Rate
Figure 7. VCC Detect Reset Output Delay
(PowerDown)
VCC
+4.75 V
+4.25 V
tR
Figure 8. VCC Detect Reset Output Delay
(PowerUp)
NCP1232
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7
PACKAGE DIMENSIONS
SO8
D SUFFIX
CASE 75106
ISSUE T
SEATING
PLANE
1
4
5
8
A
0.25
M
C B
S
S
0.25
M
B
M
h
q
C
X 45
_
L
DIM
MIN
MAX
MILLIMETERS
A
1.35
1.75
A1
0.10
0.25
B
0.35
0.49
C
0.19
0.25
D
4.80
5.00
E
1.27 BSC
e
3.80
4.00
H
5.80
6.20
h
0
7
L
0.40
1.25
q
0.25
0.50
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
E
H
A
B
e
B
A1
C
A
0.10
NCP1232
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8
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NCP1232/D
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