Semiconductor Components Industries, LLC, 2004

September, 2004- Rev. 2

Publication Order Number:

NCP1580/D

NCP1580

Low Voltage Synchronous

Buck Controller

The NCP1580 is a voltage mode PWM controller designed to

operate from a 5.0 V or 12 V supply and produce an output voltage as
low as 0.8 V. This 8-pin device provides an optimal level of
integration to reduce size and cost of the power supply. The NCP1580
has a fixed 350 kHz oscillator and soft-start function. The NCP1580
provides a 1.5 A floating gate driver design to drive N-Channel
MOSFETs in a synchronous configuration. Adaptive non-overlap
circuitry reduces switching losses by preventing simultaneous
conduction of both outputs. Protection features include thermal
shutdown and undervoltage lockout (UVLO). The NCP1580 is
available in an 8-pin SOIC package.

Features

Input Voltage Range from 4.5 V to 13.2 V

350 kHz Internal Oscillator

Boost Pin Operates to 26.5 V

Voltage Mode PWM Control

0.8 V

$1.5% Internal Reference Voltage

Adjustable Output Voltage

Internal Soft-Start

Internal 1.5 A Gate Drivers

Adaptive Non-Overlap Circuit

90% Max Duty Cycle

Input UVLO

Overtemperature Protection

Fully Specified over -40

C to 85

Applications

Graphics Cards

Desktop Computers

Servers/Networking

DSP and FPGA Power Supply

DC-DC Regulator Modules

BST

GND

COMP

SWN

OUT

Figure 1. Typical Application Diagram

SO-8

D SUFFIX

CASE 751

MARKING
DIAGRAM

PIN CONNECTIONS

= Assembly Location

= Wafer Lot

= Year

= Work Week

BST

8 PHASE

GND

7 COMP

6 FB

5 V

(Top View)

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Device

Package

Shipping

ORDERING INFORMATION

NCP1580DR2

SO-8

2500/Tape & Reel

For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

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PIN FUNCTION DESCRIPTION

Pin No.

Symbol

Description

BST

Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the
desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (C

BST

) between this

pin and the PHASE pin. Typical values for C

BST

range from 0.1

F to 1

F. Ensure that C

BST

is placed

near the IC.

Top gate MOSFET driver pin. Connect this pin to the gate of the top N-Channel MOSFET.

GND

IC ground reference. All control circuits are referenced to this pin.

Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N-Channel MOSFET.

Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1

capacitor to GND. Ensure that this decoupling capacitor is placed near the IC.

This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to
compensate the voltage-control feedback loop. Connect this pin to the output resistor divider (if used) or
directly to Vout.

COMP

Compensation Pin. This is the output of the error amplifier (EA) and the non-inverting input of the PWM
comparator. Use this pin in conjunction with the FB pin to compensate the voltage-control feedback loop.
This pin should not be shorted to ground to disable switching.

PHASE

Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the
top MOSFET. A Schottky diode between this pin and ground is recommended to reduce negative transient
voltages which is common in a power supply system.

ABSOLUTE MAXIMUM RATINGS

Pin Name

Symbol

MAX

MIN

Main Supply Voltage Input

15 V

-0.3 V

Bootstrap Supply Voltage Input

BST

30 V wrt/GND

15 V wrt/PHASE

-0.3 V

Switching Node (Bootstrap Supply Return)

PHASE

30 V

-0.7 V

High-Side Driver Output (Top Gate)

30 V wrt/GND

15 V wrt/PHASE

-0.3 V

wrt/PHASE

Low-Side Driver Output (Bottom Gate)

15 V

-0.3 V

Feedback

5.5 V

-0.3 V

COMP

5.5 V

-0.3 V

MAXIMUM RATINGS

Rating

Symbol

Value

Unit

Thermal Resistance, Junction-to-Ambient

165

C/W

Thermal Resistance, Junction-to-Case

C/W

Operating Junction Temperature Range

-40 to 150

Operating Ambient Temperature Range

-40 to 85

Storage Temperature Range

stg

-55 to +150

ESD Susceptibility

Human Body Model

Charge Device Model

2.0

200

Moisture Sensitivity Level

MSL

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

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ELECTRICAL CHARACTERISTICS

(-40

C < T

< 85

C, -40

C < T

< 125

C (Note 1), 4.5 V < V

< 13.2 V, 4.5 V < BST < 26.5 V,

= C

= 1.0 nF, for min/max values unless otherwise noted.)

Characteristic

Conditions

Min

Typ

Max

Unit

Input Voltage Range

4.5

13.2

Boost Voltage Range

4.5

26.5

Supply Current

Quiescent Supply Current

= 1.0 V, No Switching

= 13.2 V

1.0

1.75

Boost Quiescent Current

= 1.0 V, No Switching

140

Undervoltage Lockout

UVLO Threshold

Rising Edge

3.85

4.2

UVLO Hysteresis

0.5

Switching Regulator

VFB Feedback Voltage,
Control Loop in Regulation

= 0 to 70

= -40 to 85

0.788
0.784

0.800

0.812
0.816

Oscillator Frequency

288

350

412

kHz

Ramp-Amplitude Voltage

1.1

Minimum Duty Cycle

Maximum Duty Cycle

Minimum Pulse Width

Static Operating (Note 2)

100

150

nsec

Error Amplifier

DC Gain

(Note 2 )

Gain-Bandwidth Product

(Note 2)

8.0

MHz

Slew Rate

COMP_GND = 100 pF (Note 2)

2.0

4.0

FB Bias Current

VFB = 1 V (Note 2)

0.1

1.0

Gate Drivers

TG Rise Time

6.0

TG Fall Time

Load = 1.0 nF

BG Rise Time

Load = 1.0 nF

= 8.0 V

6.0

BG Fall Time

6.0

TG Sink Current

1.0

TG Source Current

= 12 V

= V

= 2 0 V

1.5

BG Sink Current

= V

= 2.0 V

(Note 2)

1.5

BG Source Current

(

)

1.5

PHASE falling to BG rising delay

= 12 V

PHASE < 2.0 V

BG > 2.0 V

BG falling to TG rising delay

= 12 V

BG < 2.0 V
TG > 2.0 V

Internal Soft-Start

Time

1.0

2.0

3.0

Thermal Shutdown

Overtemperature Trip Point

(Note 2)

160

1. Specifications to -40

C are guaranteed via correlation using standard statistical quality control (SQC), not tested in production.

2. Guaranteed by design, not tested in production.

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TYPICAL CHARACTERISTIC CURVES

400

390

380

370

360

350

340

330

320

310

410

-50

-25

100

125

150

, JUNCTION TEMPERATURE (

, FREQUENCY (kHz)

816

-50

-25

100

125

150

, JUNCTION TEMPERATURE (

REF

, REFERENCE (mV)

812

808

804

800

796

792

788

784

Figure 4. Reference Voltage (V

REF

) vs.

Temperature

Figure 5. Oscillator Frequency (f

) vs.

Temperature

300
290

= 5.0 V

= 12 V

2.15

2.10

2.05

2.00

1.95

1.90

1.85

1.80

2.20

-50

-25

100

125

150

, JUNCTION TEMPERATURE (

, SOFT-ST

T TIME (ms)

1.25

-50

-25

100

125

150

, JUNCTION TEMPERATURE (

, SUPPL

Y CURRENT (mA)

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.75

-50

-25

100

125

150

, JUNCTION TEMPERATURE (

, SUPPL

Y CURRENT (mA)

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

Figure 6. Soft-Start Time (t

) vs. Temperature

Figure 7. Quiescent Current (I

) vs. Temperature

(No Switching)

Figure 8. Quiescent Current (I

) vs. Temperature

(Switching)

100

-20

-40

-60

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

Figure 9. Error Amplifier

0.80

0.85

= 5.0 V

= 12 V

= 5.0 V

= 12 V

= 5.0 V

= 12 V

= 8.0 V

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DETAILED OPERATING DESCRIPTION

General

The NCP1580 is an 8-pin PWM controller intended for

DC-DC conversion from 5.0 V and 12 V buses. The
NCP1580 has a 1.5 A internal floating gate driver circuit
designed to drive N-Channel MOSFETs in a
synchronous-rectifier buck topology. The internal floating
gate driver simplifies design, improves performance, and
minimizes board area. The output voltage of the converter
can be precisely regulated down to 800 mV

$ 1.5% when

the V

pin is tied to V

OUT

. The switching frequency, which

is internally set to 350 kHz, and soft-start are completely
integrated. The voltage error amplifier features a 10 MHz
unity gain bandwidth and 4 V/

msec slew rate for fast

transient response.

Duty Cycle and Maximum Pulse Width Limits

In steady state DC operation, the duty cycle will stabilize

at an operating point defined by the ratio of the input to the
output voltage. The NCP1580 can achieve a 90% duty cycle.
There is a built in off-time which ensures that the bootstrap
supply is charged every cycle. The NCP1580, which is
capable of a 100 nsec minimum pulse width (typ), can allow
a 12 V to 1.0 V conversion at 350 kHz.

Input Voltage Range (V

and BST)

The input voltage range for both V

and BST is 4.5 V to

13.2 V with respect to GND and PHASE, respectively.
Although BST is rated at 13.2 V with respect to PHASE, it
can also tolerate 26.5 V with respect to GND.

Normal Shutdown Behavior

Normal shutdown occurs when the IC stops switching

because the input supply reaches UVLO threshold. In this
case, switching stops, the internal SS is discharged, and all
GATE pins go low. The switch node enters a high impedance
state and the output capacitors discharge through the load
with no ringing on the output voltage.

Internal Soft-Start

The NCP1580 features an internal soft-start function,

which reduces inrush current and overshoot of the output
voltage. Figure 10 shows a typical soft-start sequence.
Soft-start is achieved by ramping up the internal soft-start
voltage (V

) which is applied to the input of the error

amplifier. This ramp is generated by applying 0.5

mA to a

100 pf capacitor for 1

msec on every fourth clock pulse. This

sequence begins once V

surpasses its UVLO threshold

(see Figure 11). The typical soft-start time is 2 msec. The
internal soft-start voltage is held low when the part is in
UVLO.

Figure 10. Normal Startup

4.2 V

2 ms

OUT

UVLO

Startup

Normal Operation

Figure 11. Achieving Internal Soft-Start

4.2 V

5 mV

CLK

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UVLO

Undervoltage Lockout (UVLO) is provided to ensure that

unexpected behavior does not occur when V

is too low to

support the internal rails and power the converter. For the
NCP1580, the UVLO is set to ensure that the IC will start up
when V

reaches 4.2 V and shutdown when V

drops

below 3.7 V. This permits operation when converting from
a 5.0 V input voltage.

Thermal Shutdown

The NCP1580 also provides Thermal Shutdown (TSD)

for added protection. The TSD circuit monitors the die
temperature and turns off the top and bottom gate drivers if
an over temperature condition is detected. The internal soft-
start capacitor is also discharged. This is a latched state and
requires a power cycle to reset.

Drivers

The NCP1580 includes 1.5 A gate drivers to switch

external N-Channel MOSFETs. This allows the NCP1580
to address high-power as well as low-power conversion
requirements. The gate drivers also include adaptive
non-overlap circuitry. The non-overlap circuitry increases
efficiency, which minimizes power dissipation, by
minimizing the body diode conduction time.

A detailed block diagram of the non-overlap and gate

drive circuitry used in the chip is shown in Figure 12.

Careful selection and layout of external components is

required, to realize the full benefit of the onboard drivers.
The capacitors between V

and GND and between BST

and SWN must be placed as close as possible to the IC. The
current paths for the TG and BG connections must be
optimized. A ground plane should be placed on the closest
layer for return currents to GND in order to reduce loop area
and inductance in the gate drive circuit.

Figure 12. Block Diagram

UVLO

FAULT

2 V

PHASE

BST

GND

UVLO
FAULT

PWM
OUT

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APPLICATION SECTION

Input Capacitor Selection

The input capacitor has to sustain the ripple current

produced during the on time of the upper MOSFET, so it
must have a low ESR to minimize the losses. The RMS value
of this ripple is:

IinRMS

IOUT D

D) ,

where D is the duty cycle, I

inRMS

is the input RMS current,

and I

OUT

is the load current. The equation reaches its

maximum value with D = 0.5. Losses in the input capacitors
can be calculated with the following equation:

PCIN

ESRCIN

IinRMS2,

where P

CIN

is the power loss in the input capacitors and

ESR

CIN

is the effective series resistance of the input

capacitance. Due to large dI/dt through the input capacitors,
electrolytic or ceramics should be used. If a tantalum must
be used, it must be surge protected. Otherwise, capacitor
failure could occur.

Calculating Input Startup Current

To calculate the input startup current, the following

equation can be used.

Iinrush

COUT

VOUT

tSS

where I

inrush

is the input current during startup, C

OUT

the total output capacitance, V

OUT

is the desired output

voltage, and t

is the internal soft-start interval.

If the inrush current is higher than the steady state input

current during max load, then the input fuse should be rated
accordingly, if one is used.

Output Capacitor Selection

The output capacitor is a basic component for the fast

response of the power supply. In fact, during load transient,
for the first few microseconds it supplies the current to the
load. The controller immediately recognizes the load
transient and sets the duty cycle to maximum, but the current
slope is limited by the inductor value.

During a load step transient the output voltage initially

drops due to the current variation inside the capacitor and the
ESR. (neglecting the effect of the effective series inductance
(ESL)):

VOUT-ESR

+ D

IOUT

ESRCOUT,

where V

OUT-ESR

is the voltage deviation of V

OUT

due to the

effects of ESR and the ESR

COUT

is the total effective series

resistance of the output capacitors.

A minimum capacitor value is required to sustain the

current during the load transient without discharging it. The
voltage drop due to output capacitor discharge is given by
the following equation:

VOUT

DISCHARGE

IOUT2

LOUT

COUT

(VIN

VOUT)

where V

OUT-DISCHARGE

is the voltage deviation of V

OUT

due to the effects of discharge, L

OUT

is the output inductor

value and V

is the input voltage.

It should be noted that

OUT-DISCHARGE

and

OUT-ESR

are out of phase with each other, and the larger

of these two voltages will determine the maximum deviation
of the output voltage (neglecting the effect of the ESL).

Inductor Selection

Both mechanical and electrical considerations influence

the selection of an output inductor. From a mechanical
perspective, smaller inductor values generally correspond to
smaller physical size. Since the inductor is often one of the
largest components in the regulation system, a minimum
inductor value is particularly important in
space-constrained applications. From an electrical
perspective, the maximum current slew rate through the
output inductor for a buck regulator is given by:

SlewRateLOUT

VIN

VOUT

LOUT

This equation implies that larger inductor values limit the

regulator's ability to slew current through the output
inductor in response to output load transients. Consequently,
output capacitors must supply the load current until the
inductor current reaches the output load current level. This
results in larger values of output capacitance to maintain
tight output voltage regulation. In contrast, smaller values of
inductance increase the regulator's maximum achievable
slew rate and decrease the necessary capacitance, at the
expense of higher ripple current. The peak-to-peak ripple
current is given by the following equation:

Ipk-pkLOUT

VOUT(1

LOUT

350 kHZ

where Ipk-pk

LOUT

is the peak to peak current of the output.

From this equation it is clear that the ripple current increases
as L

OUT

decreases, emphasizing the trade-off between

dynamic response and ripple current.

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Feedback and Compensation

The NCP1580 allows the output of the DC-DC converter

to be adjusted from 0.8 V to 5.0 V via an external resistor
divider network. The controller will try to maintain 0.8 V at
the feedback pin. Thus, if a resistor divider circuit was
placed across the feedback pin to V

OUT

, the controller will

regulate the output voltage proportional to the resistor
divider network in order to maintain 0.8 V at the FB pin.

VOUT

Figure 13.

The relationship between the resistor divider network in

Figure 13 and the output voltage is shown in the following
equation:

VREF

VOUT

VREF

Resistor R1 is selected based on a design trade off between

efficiency and output voltage accuracy. For high values of
R1 there is less current consumption in the feedback
network, However the trade off is output voltage accuracy
due to the bias current in the error amplifier. The output
voltage error of this bias current can be estimated using the
following equation (neglecting resistor tolerance):

Error%

0.1

VREF

100%

Once R1 has been determined, R2 can be calculated.
The NCP1580 utilizes voltage mode control. This is to

say, the control loop regulates V

OUT

by monitoring V

OUT

and controlling the output current. However, since the
control loop is controlling the output current to regulate the
output voltage, there are some stability concerns since the
inductor current is 90 degrees out of phase with the voltage.
It is inherent with all voltage-mode control loops to have a
compensation network.

Figure 14. Simplified Diagram of Control Loop

OUT

-
+

RAMP

PWM
COMPARATOR

REF

OUT

ESR

The compensation network consists of the internal error

amplifier and the impedance networks Z

(R1, R3 and C3)

and Z

(R4, C1 and C2). The compensation network has to

provide a closed loop transfer function with the highest 0 dB
crossing frequency to have fast response (but always lower
than f

/8) and the highest gain in DC conditions to

minimize the load regulation. A stable control loop has a
gain crossing with -20 dB/decade slope and a phase margin
greater than 45

. Include worst-case component variations

when determining phase margin. To place the poles and
zeroes of the compensation networks, the following
equations may be used:

Modulator frequencies:

LOUT

COUT

ESR

COUT

Compensation network frequency:

)

(R1

)

R3)

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Place

, and

around the output filter resonance

; Place

at the output capacitor ESR zero

ESR

; Place

at one half of the switching frequency;

The modulator transfer function is the small-signal

transfer function of V

OUT

COMP

. This function has a

double pole at frequency

and a zero at

ESR

. The DC

Gain of the modulator is simply the input voltage V

divided by the peak-to-peak oscillator voltage

OSC

Error Amplifier

Modulator Gain

Closed Loop
Gain

Compensation
Network

ESR

Figure 15.

Visit http://www.onsemi.com/pub/Collateral/COMPCALC
for self extracting compensation program for design
assistance.

Thermal Considerations

The power dissipation of the NCP1580 varies with the

MOSFETs used, V

, and the boost voltage (V

BST

). The

average MOSFET gate current typically dominates the

control IC power dissipation. The IC power dissipation is
determined by the formula:

PIC

(ICC

VCC)

)

PTG

)

PBG.

Where:

= Control IC power dissipation,

= IC measured supply current,

= IC supply voltage,

= Top gate driver losses,

= Bottom gate driver losses.

The upper (switching) MOSFET gate driver losses are:

PTG

QTG

fSW

VBST.

Where:

= Total upper MOSFET gate charge at VBST,

= The switching frequency,

BST

= The BST pin voltage.

The lower (synchronous) MOSFET gate driver losses are:

PBG

QBG

fSW

VCC.

Where:

= total lower MOSFET gate charge at V

The junction temperature of the control IC can then be

calculated as:

)

PIC

JA.

Where:

= The junction temperature of the IC,

= The ambient temperature,

= The junction-to-ambient thermal resistance of the

IC package.

The package thermal resistance can be obtained from the

specifications section of this data sheet and a calculation can
be made to determine the IC junction temperature. However,
it should be noted that the physical layout of the board, the
proximity of other heat sources such as MOSFETs and
inductors, and the amount of metal connected to the IC,
impact the temperature of the device. Use these calculations
as a guide, but measurements should be taken in the actual
application.

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Layout Considerations

As in any high frequency switching converter, layout is

very important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding. Figure 16 shows the critical power components
of the converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be
part of ground or power plane in a printed circuit board. The
components shown in Figure 16 should be located as close
together as possible. Please note that the capacitors C

and

OUT

each represent numerous physical capacitors. It is

desirable to locate the NCP1580 within 1 inch of the
MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs'
gate and source connections from the NCP1580 must be
sized to handle up to 2.0 A peak current.

Figure 16.

OUT

PHASE

GND

NCP1580

RETURN

LOAD

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PACKAGE DIMENSIONS

SO-8

D SUFFIX

CASE 751-07

ISSUE AB

SEATING
PLANE

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751-01 THRU 751-06 ARE OBSOLETE. NEW

STANDARD IS 751-07.

0.10 (0.004)

DIM

MIN

MAX

MIN

MAX

INCHES

4.80

5.00

0.189

0.197

MILLIMETERS

3.80

4.00

0.150

0.157

1.35

1.75

0.053

0.069

0.33

0.51

0.013

0.020

1.27 BSC

0.050 BSC

0.10

0.25

0.004

0.010

0.19

0.25

0.007

0.010

0.40

1.27

0.016

0.050

0.25

0.50

0.010

0.020

5.80

6.20

0.228

0.244

-X-

-Y-

0.25 (0.010)

-Z-

0.25 (0.010)

1.52

0.060

7.0

0.275

0.6

0.024

1.270
0.050

4.0

0.155

inches

SCALE 6:1

SOLDERING FOOTPRINT

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operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NCP1580

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NCP1580