Semiconductor Components Industries, LLC, 2003
September, 2003 - Rev. 1
1
Publication Order Number:
NTD15N06/D
NTD15N06
Power MOSFET
15 Amps, 60 Volts
N-Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Typical Applications
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
MAXIMUM RATINGS
(T
J
= 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain-to-Source Voltage
V
DSS
60
Vdc
Drain-to-Gate Voltage (R
GS
= 1.0 M
W
)
V
DGR
60
Vdc
Gate-to-Source Voltage
- Continuous
- Non-repetitive (t
p
v
10 ms)
V
GS
V
GS
"
20
"
30
Vdc
Drain Current
- Continuous @ T
A
= 25
C
- Continuous @ T
A
= 100
C
- Single Pulse (t
p
v
10
m
s)
I
D
I
D
I
DM
15
10
45
Adc
Apk
Total Power Dissipation @ T
J
= 25
C
Derate above 25
C
Total Power Dissipation @ T
A
= 25
C (Note 1)
Total Power Dissipation @ T
A
= 25
C (Note 2)
P
D
48
0.32
2.1
1.5
W
W/
C
W
W
Operating and Storage Temperature Range
T
J
, T
stg
- 55 to
+175
C
Single Pulse Drain-to-Source Avalanche
Energy - Starting T
J
= 25
C
(V
DD
= 25 Vdc, V
GS
= 10 Vdc, L = 1.0 mH,
I
L(pk)
= 11 A, V
DS
= 60 Vdc)
E
AS
61
mJ
Thermal Resistance
- Junction-to-Case
- Junction-to-Ambient (Note 1)
- Junction-to-Ambient (Note 2)
R
q
JC
R
q
JA
R
q
JA
3.13
71.4
100
C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8
from case for 10 seconds
T
L
260
C
1. When surface mounted to an FR4 board using 0.5 sq. in. pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
15 AMPERES
60 VOLTS
R
DS(on)
= 76 m
W
(
TYP)
Device
Package
Shipping
ORDERING INFORMATION
NTD15N06
DPAK
75 Units/Rail
http://onsemi.com
N-Channel
D
S
G
NTD15N06-1
DPAK
Straight Lead
75 Units/Rail
NTD15N06T4
DPAK
2500/Tape & Reel
1
Gate
3
Source
2
Drain
4
Drain
DPAK
CASE 369C
(Surface Mount)
Style 2
MARKING DIAGRAMS
15N06
Device Code
Y
= Year
WW
= Work Week
YWW
15N06
1 2
3
4
YWW
15N06
1
Gate
3
Source
2
Drain
4
Drain
DPAK
CASE 369D
(Straight Lead)
Style 2
1
2
3
4
NTD15N06
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS
(T
J
= 25
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage (Note 3)
(V
GS
= 0 Vdc, I
D
= 250
m
Adc)
Temperature Coefficient (Positive)
V
(BR)DSS
60
-
68
54.4
-
-
Vdc
mV/
C
Zero Gate Voltage Drain Current
(V
DS
= 60 Vdc, V
GS
= 0 Vdc)
(V
DS
= 60 Vdc, V
GS
= 0 Vdc, T
J
= 150
C)
I
DSS
-
-
-
-
1.0
10
m
Adc
Gate-Body Leakage Current (V
GS
=
20
Vdc, V
DS
= 0 Vdc)
I
GSS
-
-
100
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(V
DS
= V
GS
, I
D
= 250
m
Adc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
-
2.9
6.3
4.0
-
Vdc
mV/
C
Static Drain-to-Source On-Resistance (Note 3)
(V
GS
= 10 Vdc, I
D
= 7.5 Adc)
R
DS(on)
-
76
90
m
W
Static Drain-to-Source On-Voltage (Note 3)
(V
GS
= 10 Vdc, I
D
= 15 Adc)
(V
GS
= 10 Vdc, I
D
= 7.5 Adc, T
J
= 150
C)
V
DS(on)
-
-
1.2
1.08
1.62
-
Vdc
Forward Transconductance (Note 3) (V
DS
= 7.0 Vdc, I
D
= 6.0 Adc)
g
FS
-
6.7
-
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
-
325
450
pF
Output Capacitance
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
oss
-
108
150
Transfer Capacitance
f = 1.0 MHz)
C
rss
-
34
70
SWITCHING CHARACTERISTICS (Note 4)
Turn-On Delay Time
t
d(on)
-
10
15
ns
Rise Time
(V
DD
= 48 Vdc, I
D
= 15 Adc,
t
r
-
25
70
Turn-Off Delay Time
(V
DD
= 48 Vdc, I
D
= 15 Adc,
V
GS
= 10 Vdc, R
G
= 9.1
W
) (Note 3)
t
d(off)
-
14
50
Fall Time
t
f
-
13
50
Gate Charge
Q
T
-
12
20
nC
(V
DS
= 48 Vdc, I
D
= 15 Adc,
V
GS
= 10 Vdc) (Note 3)
Q
1
-
4.1
-
V
GS
= 10 Vdc) (Note 3)
Q
2
-
4.5
-
SOURCE-DRAIN DIODE CHARACTERISTICS
Forward On-Voltage
(I
S
= 15 Adc, V
GS
= 0 Vdc) (Note 3)
(I
S
= 15 Adc, V
GS
= 0 Vdc, T
J
= 150
C)
V
SD
-
-
0.96
0.83
1.15
-
Vdc
Reverse Recovery Time
t
rr
-
35
-
ns
(I
S
= 15 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/
m
s) (Note 3)
t
a
-
27
-
dI
S
/dt = 100 A/
m
s) (Note 3)
t
b
-
7.4
-
Reverse Recovery Stored Charge
Q
RR
-
0.050
-
m
C
3. Pulse Test: Pulse Width
300
m
s, Duty Cycle
2%.
4. Switching characteristics are independent of operating junction temperatures.
NTD15N06
http://onsemi.com
3
0
16
8
24
32
4
12
20
28
2
1.6
1.2
1.4
1
0.8
0.6
10
1
1000
0
5
2
1
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
I
D
, DRAIN CURRENT (AMPS)
0
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
I
D
, DRAIN CURRENT (AMPS)
0
16
8
0.08
0
24
Figure 3. On-Resistance versus Drain Current
I
D
, DRAIN CURRENT (AMPS)
Figure 4. On-Resistance versus Drain Current
I
D
, DRAIN CURRENT (AMPS)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (
W
)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (
W
)
Figure 5. On-Resistance Variation with
Temperature
T
J
, JUNCTION TEMPERATURE (
C)
Figure 6. Drain-to-Source Leakage Current
versus Voltage
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE
(NORMALIZED)
I
DSS
, LEAKAGE (nA)
32
-50
50
25
0
-25
75
125
100
3
4
8
0
40
30
20
60
10
3
8
16
9 V
8 V
7 V
6 V
5.5 V
V
DS
10 V
T
J
= 25
C
T
J
= -55
C
T
J
= 100
C
T
J
= 100
C
V
GS
= 10 V
V
GS
= 15 V
150
175
V
GS
= 0 V
I
D
= 7.5 A
V
GS
= 10 V
24
0.16
0.2
6.5 V
V
GS
= 10 V
T
J
= 25
C
T
J
= -55
C
T
J
= 100
C
32
T
J
= 150
C
T
J
= 100
C
0
32
8
16
24
6
5 V
T
J
= 25
C
T
J
= -55
C
50
100
5
1.8
4
4.5 V
7
4
12
20
28
0.04
0.12
0.08
0
0.16
0.2
0.04
0.12
NTD15N06
http://onsemi.com
4
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain-gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
- V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn-on and turn-off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
- V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off-state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on-state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
C
rss
10
0
10
15
20
25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE (pF)
Figure 7. Capacitance Variation
900
600
0
V
GS
V
DS
200
5
5
V
GS
= 0 V
V
DS
= 0 V
C
iss
C
oss
C
rss
C
iss
400
800
100
300
500
700
T
J
= 25
C
NTD15N06
http://onsemi.com
5
I
S
, SOURCE CURRENT (AMPS)
t, TIME (ns)
V
GS
, GA
TE-T
O-SOURCE VOL
T
AGE (VOL
TS)
16
0
0.6
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
V
SD
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 8. Gate-To-Source and Drain-To-Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
R
G
, GATE RESISTANCE (
W
)
1
10
100
100
1
V
GS
= 0 V
T
J
= 25
C
Figure 10. Diode Forward Voltage versus Current
0
2
0
Q
G
, TOTAL GATE CHARGE (nC)
12
4
6
2
4
12
0.68
0.76
1
4
8
12
I
D
= 15 A
T
J
= 25
C
V
GS
Q
2
Q
1
Q
T
t
r
t
d(off)
t
d(on)
t
f
10
V
DS
= 30 V
I
D
= 15 A
V
GS
= 10 V
0.84
0.92
8
10
6
8
10
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain-to-source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25
C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal Resistance -
General Data and Its Use."
Switching between the off-state and the on-state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the
transition time (t
r
,t
f
) do not exceed 10
ms. In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
- T
C
)/(R
qJC
).
A Power MOSFET designated E-FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non-linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E-FETs can withstand the stress of
drain-to-source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous I
D
can safely be assumed to
equal the values indicated.
NTD15N06
http://onsemi.com
6
SAFE OPERATING AREA
E
AS
, SINGLE PULSE DRAIN-T
O-SOURCE
A
V
ALANCHE ENERGY (mJ)
I
D
, DRAIN CURRENT (AMPS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
T
J
, STARTING JUNCTION TEMPERATURE (
C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
0.1
1
100
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 13. Thermal Response
1
100
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0
25
50
75
100
125
20
I
D
= 11 A
10
10
175
Figure 14. Diode Reverse Recovery Waveform
di/dt
t
rr
t
a
t
p
I
S
0.25 I
S
TIME
I
S
t
b
40
80
V
GS
= 20 V
SINGLE PULSE
T
C
= 25
C
1 ms
100
m
s
10 ms
dc
10
m
s
150
r(t)
, EFFECTIVE
TRANSIENT
THERMAL
RESIST
ANCE
(NORMALIZED)
t, TIME (
m
s)
0.1
1.0
0.01
0.1
0.2
0.02
D = 0.5
0.05
0.01
SINGLE PULSE
R
q
JC
(t) = r(t) R
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
C
= P
(pk)
R
q
JC
(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
1
10
0.1
0.01
0.001
0.0001
0.00001
60
NTD15N06
http://onsemi.com
7
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
DPAK
5.80
0.228
2.58
0.101
1.6
0.063
6.20
0.244
3.0
0.118
6.172
0.243
mm
inches
SCALE 3:1
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
surface mount device is determined by T
J(max)
, the
maximum rated junction temperature of the die, R
JA
, the
thermal resistance from the device junction to ambient, and
the operating temperature, T
A
. Using the values provided
on the data sheet, P
D
can be calculated as follows:
P
D
=
T
J(max)
- T
A
R
JA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature T
A
of 25
C,
one can calculate the power dissipation of the device. For a
DPAK device, P
D
is calculated as follows.
P
D
=
175
C - 25
C
71.4
C/W
= 2.1 Watts
The 71.4
C/W for the DPAK package assumes the use of
0.5 sq. in. source pad on a glass epoxy printed circuit board
to achieve a power dissipation of 2.1 W. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which
can defeat the purpose of using surface mount technology.
For example, a graph of R
JA
versus drain pad area is shown
in Figure 15.
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
2.1 Watts
Board Material = 0.0625
G-10/FR-4, 2 oz Copper
80
100
60
40
20
10
8
6
4
2
0
3.6 Watts
6.0 Watts
T
A
= 25
C
A, AREA (SQUARE INCHES)
T
O
AMBIENT
(
C/W)
R
JA
,
THERMAL
RESIST
ANCE, JUNCTION
NTD15N06
http://onsemi.com
8
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143,
SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D
2
PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
"tombstoning" may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 16 shows a
typical stencil for the DPAK and D
2
PAK packages. The
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
Figure 16. Typical Stencil for DPAK and
D
2
PAK Packages
SOLDER PASTE
OPENINGS
STENCIL
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100
C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10
C.
The soldering temperature and time shall not exceed
260
C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5
C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied
during cooling.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* * Due to shadowing and the inability to set the wave
height to incorporate other surface mount components, the
D
2
PAK is not recommended for wave soldering.
NTD15N06
http://onsemi.com
9
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating "profile" for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 17 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177 -189
C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joint.
STEP 1
PREHEAT
ZONE 1
"RAMP"
STEP 2
VENT
"SOAK"
STEP 3
HEATING
ZONES 2 & 5
"RAMP"
STEP 4
HEATING
ZONES 3 & 6
"SOAK"
STEP 5
HEATING
ZONES 4 & 7
"SPIKE"
STEP 6
VENT
STEP 7
COOLING
200
C
150
C
100
C
5
C
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
205
TO 219
C
PEAK AT
SOLDER
JOINT
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
100
C
150
C
160
C
170
C
140
C
Figure 17. Typical Solder Heating Profile
NTD15N06
http://onsemi.com
10
PACKAGE DIMENSIONS
DPAK
CASE 369C-01
ISSUE O
D
A
K
B
R
V
S
F
L
G
2 PL
M
0.13 (0.005)
T
E
C
U
J
H
-T-
SEATING
PLANE
Z
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.235
0.245
5.97
6.22
B
0.250
0.265
6.35
6.73
C
0.086
0.094
2.19
2.38
D
0.027
0.035
0.69
0.88
E
0.018
0.023
0.46
0.58
F
0.037
0.045
0.94
1.14
G
0.180 BSC
4.58 BSC
H
0.034
0.040
0.87
1.01
J
0.018
0.023
0.46
0.58
K
0.102
0.114
2.60
2.89
L
0.090 BSC
2.29 BSC
R
0.180
0.215
4.57
5.45
S
0.025
0.040
0.63
1.01
U
0.020
---
0.51
---
V
0.035
0.050
0.89
1.27
Z
0.155
---
3.93
---
1
2
3
4
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
DPAK
CASE 369D-01
ISSUE O
1
2
3
4
V
S
A
K
-T-
SEATING
PLANE
R
B
F
G
D
3 PL
M
0.13 (0.005)
T
C
E
J
H
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.235
0.245
5.97
6.35
B
0.250
0.265
6.35
6.73
C
0.086
0.094
2.19
2.38
D
0.027
0.035
0.69
0.88
E
0.018
0.023
0.46
0.58
F
0.037
0.045
0.94
1.14
G
0.090 BSC
2.29 BSC
H
0.034
0.040
0.87
1.01
J
0.018
0.023
0.46
0.58
K
0.350
0.380
8.89
9.65
R
0.180
0.215
4.45
5.45
S
0.025
0.040
0.63
1.01
V
0.035
0.050
0.89
1.27
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Z
Z
0.155
---
3.93
---
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
NTD15N06/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
PDF 
ZIP