Semiconductor Components Industries, LLC, 2002
May, 2002 Rev. 3
1
Publication Order Number:
SL05T1/D
SL05T1 Series
300 Watt, SOT-23 Low
Capacitance TVS for High
Speed Line Protections
This new family of TVS offers transient overvoltage protection with
significantly reduced capacitance. The capacitance is lowered by
integrating a compensating diode in series. This integrated solution
offers ESD protection for high speed interfaces such as communication
systems, computers, and computer peripherals.
Specification Features:
TVS Diode in Series with a Compensating Diode Offers <5 pF
Capacitance
ESD Protection Meeting IEC 6100042, 44, 45
Peak Power Rating of 300 Watts, 8
20
ms
BiDirection Protection Can Be Achieved By Using Two Devices
Flammability Rating UL 94 V0
Mechanical Characteristics:
CASE:
Void-free, transfer-molded, thermosetting plastic case
FINISH:
Corrosion resistant finish, easily solderable
MAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES:
260
C for 10 Seconds
Package designed for optimal automated board assembly
Small package size for high density applications
Available in 8 mm Tape and Reel
Use the Device Number to order the 7 inch/3,000 unit reel.
Replace the "T1" with "T3" in the Device Number to order the
13 inch/10,000 unit reel.
SOT23
CASE 318
STYLE 26
2
1
3
(NC)
1
2
3
Device
Package
Shipping
ORDERING INFORMATION
SL05T1
SOT23
3000/Tape & Reel
SL15T1
SOT23
3000/Tape & Reel
SL24T1
SOT23
3000/Tape & Reel
xxx
MARKING
DIAGRAM
xxx
= Device Code
M
= Date Code
M
See specific marking information in the device marking
column of the table on page 3 of this data sheet.
DEVICE MARKING INFORMATION
SL05T3
SOT23
10,000/Tape & Reel
SL15T3
SOT23
10,000/Tape & Reel
SL24T3
SOT23
10,000/Tape & Reel
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SL05T1 Series
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2
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Peak Power Dissipation @ 8x20 usec (Note 1)
@ T
L
25
C
P
pk
300
W
IEC 6100042
Level 4
Contact Discharge
Air Discharge
IEC 6100044
EFT
IEC 6100045
Lightning
V
pp
8
16
40
12
kV
kV
Amps
Amps
Total Power Dissipation on FR5 Board (Note 2) @ T
A
= 25
C
Derate above 25
C
P
D
225
1.8
mW
mW/
C
Thermal Resistance Junction to Ambient
R
q
JA
556
C/W
Total Power Dissipation on Alumina Substrate (Note 3) @ T
A
= 25
C
Derate above 25
C
P
D
300
2.4
mW
mW/
C
Thermal Resistance Junction to Ambient
R
q
JA
417
C/W
Junction and Storage Temperature Range
T
J
, T
stg
55 to +150
C
Lead Solder Temperature Maximum (10 Second Duration)
T
L
260
C
1. Nonrepetitive current pulse per Figure 2
2. FR5 = 1.0 x 0.75 x 0.62 in.
3. Alumina = 0.4 x 0.3 x 0.024 in., 99.5% alumina
ELECTRICAL CHARACTERISTICS
(T
A
= 25
C unless otherwise noted)
UNIDIRECTIONAL
(Circuit tied to Pins 1 and 3 or 2 and 3)
Symbol
Parameter
I
PP
Maximum Reverse Peak Pulse Current
V
C
Clamping Voltage @ I
PP
V
RWM
Working Peak Reverse Voltage
I
R
Maximum Reverse Leakage Current @ V
RWM
V
BR
Breakdown Voltage @ I
T
I
T
Test Current
Q
V
BR
Maximum Temperature Coefficient of V
BR
I
F
Forward Current
V
F
Forward Voltage @ I
F
Z
ZT
Maximum Zener Impedance @ I
ZT
I
ZK
Reverse Current
Z
ZK
Maximum Zener Impedance @ I
ZK
UniDirectional TVS
I
PP
I
F
V
I
I
R
I
T
V
RWM
V
C
V
BR
V
F
SL05T1 Series
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3
ELECTRICAL CHARACTERISTICS
Breakdown Voltage
(Note 4)
V
C
, Clamping Voltage
(Note 5)
Max
Capacitance
Device
V
RWM
I
R
@ V
RWM
V
BR
@ 1 mA (Volts)
@ 1 Amp
@ 5 Amp
Max
I
PP
@ V
R
= 0 V, 1 MHz (pF)
Device
Device
Marking
(Volts)
(
m
A)
Min
Max
(Volts)
(Volts)
(Amps)
Typ
Max
SL05
L05
5.0
20
6.0
8.0
9.8
11
17
3.5
5.0
SL15
L15
15
1.0
16.7
18.5
24
30
10
3.5
5.0
SL24
L24
24
1.0
26.7
29
43
55
5.0
3.5
5.0
4. V
BR
measured at pulse test current of 1 mA at an ambient temperature of 25
C
5. Surge current waveform per Figure 2
TYPICAL CHARACTERISTICS
0.1
10
10
Figure 1. Maximum Peak Power Rating
1
PULSE WIDTH (
m
s)
100
1000
1
0.1
0.01
Figure 2. 8
20
m
s Pulse Waveform
P
PK
, PEAK POWER (kW)
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
t, TIME (
m
s)
% OF PEAK PULSE CURRENT
t
P
t
r
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8
m
s
PEAK VALUE I
RSM
@ 8
m
s
HALF VALUE I
RSM
/2 @ 20
m
s
80
Figure 3. Typical Junction Capacitance
55
25
150
10
1
0.1
0.01
Figure 4. Typical Leakage Over Temperature
TEMPERATURE (
C)
@ 50% V
RWM
4
3.5
3
2
1.5
0.5
0
C, CAP
ACIT
ANCE (pF), 1 MHz FREQ.
2.5
1
@ ZERO BIAS
@ V
RWM
SL05
SL15
SL24
LEAKAGE (
m
A)
SL05T1
SL05T1 Series
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4
INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT23 POWER DISSIPATION
The power dissipation of the SOT23 is a function of the
drain pad size. This can vary from the minimum pad size
for soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by T
J(max)
, the maximum rated junction
temperature of the die, R
qJA
, the thermal resistance from
the device junction to ambient, and the operating
temperature, T
A
. Using the values provided on the data
sheet for the SOT23 package, P
D
can be calculated as
follows:
P
D
=
T
J(max)
T
A
R
q
JA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature T
A
of 25
C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
P
D
= 150
C 25
C = 225 milliwatts
556
C/W
The 556
C/W for the SOT23 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 225
milliwatts. There are other alternatives to achieving higher
power dissipation from the SOT23 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad
. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100
C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10
C.
The soldering temperature and time shall not exceed
260
C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5
C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied
during cooling.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
SL05T1 Series
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5
Applications Background
This new family of TVS devices (SL05T1 series) are
designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD conditions or
transient voltage conditions. Because of their low
capacitance value (less than 5 pF), they can be used in high
speed I/O data lines. Low capacitance is achieved by
integrating a compensating diode in series with the TVS
which is basically based in the below theoretical principle:
Capacitance in parallel: CT = C1+C2+....+Cn
Capacitance in series: 1/CT = (1/C1)+(1/C2)+....+(1/Cn)
The Figure 5 shows the integrated solution of the SL05T1
series device:
Figure 5.
COMPENSATING
DIODE
TVS
In the case that an overvoltage condition occurs in the I/O
line protected by the SL05T1 series device, the TVS is
reversedbiased while the compensation diode is
forwardbiased so the resulting current due to the transient
voltage is drained to ground.
If protection in both polarities is required, an additional
device is connected in inverseparallel with reference to the
first one, the Figure 6 illustrates the inverseparallel
connection for bidirectional or unidirectional lines:
Figure 6.
3
2
1
3
2
1
An alternative solution to protect unidirectional lines, is to
connect a fast switching steering diode in parallel with the
SL05T1 series device. When the steering diode is
forwardbiased, the TVS will avalanche and conduct in
reverse direction. It is important to note that by adding a
steering diode, the effective capacitance in the circuit will be
increased, therefore the impact of adding a steering diode
must be taken in consideration to establish whether the
incremental capacitance will affect the circuit functionality
or not. The Figure 7 shows the connection between the
steering diode and the SL05T1 series device:
Figure 7.
STEERING DIODE
SL05T1 DEVICE
Another typical application in which the SL05T1 series
device can be utilized, is to protect multiple I/O lines. The
protection in each of the I/O lines is achieved by connecting
two devices in inverseparallel. The Figure 8 illustrates how
multiple I/O line protection is achieved:
Figure 8.
OUTPUT
INPUT
For optimizing the protection, it is recommended to use ground planes and short path lengths to minimize the PCB's ground inductance.
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