Semiconductor Components Industries, LLC, 2005
March, 2005 - Rev. 21
1
Publication Order Number:
TL431/D
TL431, A, B Series,
NCV431A
Programmable
Precision References
The TL431, A, B integrated circuits are three-terminal
programmable shunt regulator diodes. These monolithic IC voltage
references operate as a low temperature coefficient zener which is
programmable from V
ref
to 36 V with two external resistors. These
devices exhibit a wide operating current range of 1.0 mA to 100 mA
with a typical dynamic impedance of 0.22
W. The characteristics of
these references make them excellent replacements for zener diodes in
many applications such as digital voltmeters, power supplies, and op
amp circuitry. The 2.5 V reference makes it convenient to obtain a
stable reference from 5.0 V logic supplies, and since the TL431, A, B
operates as a shunt regulator, it can be used as either a positive or
negative voltage reference.
Features
Programmable Output Voltage to 36 V
Voltage Reference Tolerance:
0.4%, Typ @ 25
C (TL431B)
Low Dynamic Output Impedance, 0.22
W Typical
Sink Current Capability of 1.0 mA to 100 mA
Equivalent Full-Range Temperature Coefficient of 50 ppm/
C
Typical
Temperature Compensated for Operation over Full Rated Operating
Temperature Range
Low Output Noise Voltage
Pb-Free Packages are Available
(Top
View)
3
1
Reference
N/C
N/C
N/C
2
4
8
7
6
5 N/C
Anode
N/C
Cathode
Anode
Anode
TO-92 (TO-226)
LP SUFFIX
CASE 29
PDIP-8
P SUFFIX
CASE 626
SOIC-8
D SUFFIX
CASE 751
Pin 1. Reference
2. Anode
3. Cathode
(Top View)
3
1
Reference
N/C
2
4
8
7
6
5
N/C
Cathode
Micro8
E
DM SUFFIX
CASE 846A
8
1
8
1
8
1
1
2
3
This is an internally modified SOIC-8 package. Pins 2, 3, 6 and
7 are electrically common to the die attach flag. This internal
lead frame modification increases power dissipation capability
when appropriately mounted on a printed circuit board. This
modified package conforms to all external dimensions of the
standard SOIC-8 package.
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See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 15 of this data sheet.
DEVICE MARKING INFORMATION
TL431, A, B Series, NCV431A
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2
Representative Block Diagram
1.0 k
Cathode
(K)
2.5 V
ref
Anode (A)
Reference
(R)
4.0 k
150
Symbol
10 k
20 pF
800
Cathode (K)
3.28 k
Representative Schematic Diagram
Component values are nominal
Anode (A)
-
+
Anode
(A)
800
Reference
(R)
2.4 k
7.2 k
20 pF
800
Cathode
(K)
Reference
(R)
This device contains 12 active transistors.
MAXIMUM RATINGS
(Full operating ambient temperature range applies, unless
otherwise noted.)
Rating
Symbol
Value
Unit
Cathode to Anode Voltage
V
KA
37
V
Cathode Current Range, Continuous
I
K
-100 to +150
mA
Reference Input Current Range, Continuous
I
ref
-0.05 to +10
mA
Operating Junction Temperature
T
J
150
C
Operating Ambient Temperature Range
T
A
C
TL431I, TL431AI, TL431BI
A
-40 to +85
C
TL431C, TL431AC, TL431BC
0 to +70
NCV431AI, TL431BV
-40 to +125
Storage Temperature Range
T
stg
-65 to +150
C
Total Power Dissipation @ T
A
= 25
C
P
D
W
Derate above 25
C Ambient Temperature
D, LP Suffix Plastic Package
0.70
P Suffix Plastic Package
1.10
DM Suffix Plastic Package
0.52
Total Power Dissipation @ T
C
= 25
C
P
D
W
Derate above 25
C Case Temperature
D, LP Suffix Plastic Package
1.5
P Suffix Plastic Package
3.0
NOTE:
ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Condition
Symbol
Min
Max
Unit
Cathode to Anode Voltage
V
KA
V
ref
36
V
Cathode Current
I
K
1.0
100
mA
THERMAL CHARACTERISTICS
Characteristic
Symbol
D, LP Suffix
Package
P Suffix
Package
DM Suffix
Package
Unit
Thermal Resistance, Junction-to-Ambient
R
q
JA
178
114
240
C/W
Thermal Resistance, Junction-to-Case
R
q
JC
83
41
-
C/W
TL431, A, B Series, NCV431A
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3
ELECTRICAL CHARACTERISTICS
(T
A
= 25
C, unless otherwise noted.)
TL431I
TL431C
Characteristic
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Reference Input Voltage (Figure 1)
V
KA
= V
ref
, I
K
= 10 mA
T
A
= 25
C
T
A
= T
low
to T
high
(Note 1)
V
ref
2.44
2.41
2.495
-
2.55
2.58
2.44
2.423
2.495
-
2.55
2.567
V
High Logic Level Supply Current from V
CC
I
CCH
60
-
45
60
mA
mA
mA
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 1, 2)
V
KA
= V
ref,
I
K
= 10 mA
D
V
ref
-
7.0
30
-
3.0
17
mV
Ratio of Change in Reference Input Voltage to Change
in Cathode to Anode Voltage
I
K
= 10 mA (Figure 2),
D
V
KA
= 10 V to V
ref
D
V
KA
= 36 V to 10 V
D
V
ref
D
V
KA
-
-
-1.4
-1.0
-2.7
-2.0
-
-
-1.4
-1.0
-2.7
-2.0
mV/V
Reference Input Current (Figure 2)
I
K
= 10 mA, R1 = 10 k, R2 =
T
A
= 25
C
T
A
= T
low
to T
high
(Note 1)
I
ref
-
-
1.8
-
4.0
6.5
-
-
1.8
-
4.0
5.2
m
A
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 1, 4)
I
K
= 10 mA, R1 = 10 k, R2 =
D
I
ref
-
0.8
2.5
-
0.4
1.2
m
A
Minimum Cathode Current For Regulation
V
KA
= V
ref
(Figure 1)
I
min
-
0.5
1.0
-
0.5
1.0
mA
Off-State Cathode Current (Figure 3)
V
KA
= 36 V, V
ref
= 0 V
I
off
-
20
1000
-
20
1000
nA
Dynamic Impedance (Figure 1, Note 3)
V
KA
= V
ref
,
D
I
K
= 1.0 mA to 100 mA
f
1.0 kHz
|Z
KA
|
-
0.22
0.5
-
0.22
0.5
W
1. T
low
= -40
C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM;
= 0
C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM,
TL431ACDM, TL431BCDM
T
high
= +85
C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM
= +70
C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM,
TL431BCDM
2. The deviation parameter
D
V
ref
is defined as the difference between the maximum and minimum values obtained over the full operating
ambient temperature range that applies.
DV
ref
= V
ref
max
-V
ref
min
DT
A
= T
2
- T
1
T2
Ambient Temperature
T1
V
ref
min
V
ref
max
The average temperature coefficient of the reference input voltage,
a
V
ref
is defined as:
V
ref
ppm
_
C
+
D
V
ref
V
ref
@ 25
_
C
X 106
D
T
A
+
D
V
ref
x 106
D
T
A
(V
ref
@ 25
_
C)
a
V
ref
can be positive or negative depending on whether V
ref
Min or V
ref
Max occurs at the lower ambient temperature. (Refer to Figure 6.)
Example :
D
V
ref
+
8.0 mV and slope is positive,
V
ref
@ 25
_
C
+
2.495 V,
D
T
A
+
70
_
C
a
V
ref
+
0.008 x 106
70 (2.495)
+
45.8 ppm
_
C
3. The dynamic impedance Z
KA
is defined as:
|Z
KA
|
+
D
V
KA
D
I
K
. When the device is programmed with two external resistors, R1 and R2,
(refer to Figure 2) the total dynamic impedance of the circuit is defined as:
|Z
KA
|
[
|Z
KA
|
1
)
R1
R2
TL431, A, B Series, NCV431A
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4
ELECTRICAL CHARACTERISTICS
(T
A
= 25
C, unless otherwise noted.)
TL431AI / NCV431AI
TL431AC
TL431BI / TL431BV
Characteristic
Symbol
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Reference Input Voltage (Figure 1)
V
ref
V
Reference In ut Voltage (Figure 1)
V
KA
= V
ref
, I
K
= 10 mA
T
25 C
V
ref
2 47
2 495
2 52
2 47
2 495
2 52
2 483
2 495
2 507
V
V
KA
V
ref
, I
K
10 mA
T
A
= 25
C
T
T
t T
2.47
2 44
2.495
2.52
2 55
2.47
2 453
2.495
2.52
2 537
2.483
2 475
2.495
2 495
2.507
2 515
A
T
A
= T
low
to T
high
2.44
-
2.55
2.453
-
2.537
2.475
2.495
2.515
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 4, 5)
V
KA
= V
ref,
I
K
= 10 mA
D
V
ref
-
7.0
30
-
3.0
17
-
3.0
17
mV
Ratio of Change in Reference Input Voltage to
Change in Cathode to Anode Voltage
I
K
= 10 mA (Figure 2),
D
V
KA
= 10 V to V
ref
D
V
KA
= 36 V to 10 V
D
V
ref
D
V
KA
-
-
-1.4
-1.0
-2.7
-2.0
-
-
-1.4
-1.0
-2.7
-2.0
-
-
-1.4
-1.0
-2.7
-2.0
mV/V
Reference Input Current (Figure 2)
I
K
= 10 mA, R1 = 10 k, R2 =
T
A
= 25
C
T
A
= T
low
to T
high
(Note 4)
I
ref
-
-
1.8
-
4.0
6.5
-
-
1.8
-
4.0
5.2
-
-
1.1
-
2.0
4.0
m
A
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 4)
I
K
= 10 mA, R1 = 10 k, R2 =
D
I
ref
-
0.8
2.5
-
0.4
1.2
-
0.8
2.5
m
A
Minimum Cathode Current For Regulation
V
KA
= V
ref
(Figure 1)
I
min
-
0.5
1.0
-
0.5
1.0
-
0.5
1.0
mA
Off-State Cathode Current (Figure 3)
V
KA
= 36 V, V
ref
= 0 V
I
off
-
20
1000
-
20
1000
-
0.23
500
nA
Dynamic Impedance (Figure 1, Note 6)
V
KA
= V
ref
,
D
I
K
= 1.0 mA to 100 mA
f
1.0 kHz
|Z
KA
|
-
0.22
0.5
-
0.22
0.5
-
0.14
0.3
W
4. T
low
= -40
C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431BV, TL431AIDM, TL431IDM,
TL431BIDM, NCV431AIDMR2, NCV431AIDR2
= 0
C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM,
TL431ACDM, TL431BCDM
T
high
= +85
C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM
= +70
C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM,
TL431BCDM
= +125
C TL431BV, NCV431AIDMR2, NCV431AIDR2
5. The deviation parameter
D
V
ref
is defined as the difference between the maximum and minimum values obtained over the full operating
ambient temperature range that applies.
DV
ref
= V
ref
max
-V
ref
min
DT
A
= T
2
- T
1
T2
Ambient Temperature
T1
V
ref
min
V
ref
max
The average temperature coefficient of the reference input voltage,
a
V
ref
is defined as:
V
ref
ppm
_
C
+
D
V
ref
V
ref
@ 25
_
C
X 106
D
T
A
+
D
V
ref
x 106
D
T
A
(V
ref
@ 25
_
C)
a
V
ref
can be positive or negative depending on whether V
ref
Min or V
ref
Max occurs at the lower ambient temperature. (Refer to Figure 6.)
Example :
D
V
ref
+
8.0 mV and slope is positive,
V
ref
@ 25
_
C
+
2.495 V,
D
T
A
+
70
_
C
a
V
ref
+
0.008 x 106
70 (2.495)
+
45.8 ppm
_
C
6. The dynamic impedance Z
KA
is defined as
|Z
KA
|
+
D
V
KA
D
I
K
When the device is programmed with two external resistors, R1 and R2, (refer
to Figure 2) the total dynamic impedance of the circuit is defined as:
|Z
KA
|
[
|Z
KA
|
1
)
R1
R2
7. NCV431AIDMR2, NCV431AIDR2 T
low
= -40
C, T
high
= +125
C. Guaranteed by design. NCV prefix is for automotive and other applications
requiring site and change control.
TL431, A, B Series, NCV431A
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5
I
K
V
ref
V
KA
Input
Figure 1. Test Circuit for V
KA
= V
ref
Input
I
K
R2
I
ref
V
ref
V
KA
R1
Figure 2. Test Circuit for V
KA
> V
ref
V
KA
+ V
ref
1
) R1
R2
) I
ref S
R1
I
off
Input
V
KA
Figure 3. Test Circuit for I
off
-1.0
I
Min
200
400
V
KA
, CATHODE VOLTAGE (V)
-200
0
0
1.0
2.0
3.0
800
600
-2.0
-1.0
0
-100
1.0
2.0
3.0
150
50
V
KA
, CATHODE VOLTAGE (V)
0
-50
Figure 4. Cathode Current versus
Cathode Voltage
Figure 5. Cathode Current versus
Cathode Voltage
Input
100
V
KA
= V
ref
T
A
= 25
C
I
K
V
KA
I K
, CA
THODE CURRENT
(mA)
I K
, CA
THODE CURRENT
(
A
)
125
T
A
, AMBIENT TEMPERATURE (
C)
3.0
100
50
75
-55
0
2.5
0.5
2.0
1.0
25
0
-25
1.5
2600
2580
2560
2540
2520
2500
2480
2460
V
KA
= V
ref
I
K
= 10 mA
T
A
, AMBIENT TEMPERATURE (
C)
V
KA
I
K
-55
Input
V
ref
75
100
125
2440
0
50
Figure 6. Reference Input Voltage versus
Ambient Temperature
Figure 7. Reference Input Current versus
Ambient Temperature
2420
2400
25
-25
Input
I
K
I
K
= 10 mA
I
ref
10k
V
KA
ref
V
,
REFERENCE INPUT
VOL
T
AGE (mV)
I ref
, REFERENCE INPUT
CURRENT
(
A
)
V
ref
Max = 2550 mV
V
ref
Typ = 2495 mV
V
ref
Min = 2440 mV
V
KA
= V
ref
T
A
= 25
C
Input
V
KA
I
K
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6
NOISE VOL
T
AGE (nV/
Hz)
-55
f, FREQUENCY (MHz)
100
10
1.0
100 k
10 M
1.0 M
1.0 k
10 k
0.1
75
-25
0
25
50
100
125
T
A
, AMBIENT TEMPERATURE (
C)
0.200
0.220
0.240
0.300
0.320
0.260
0.280
I
K
50
-
1.0 k
+
Output
GND
Output
GND
I
K
50
-
1.0 k
+
V
KA
= V
ref
D I
K
= 1.0 mA to 100 mA
f
1.0 kHz
T
A
= 25
C
D I
K
= 1.0 mA to 100 mA
|Z
KA
|, DYNAMIC IMPEDANCE (
)
|Z
KA
|, DYNAMIC IMPEDANCE (
)
f, FREQUENCY (Hz)
40
10
10 k
1.0 k
100
0
20
100 k
60
f, FREQUENCY (MHz)
100 k
0
10 M
1.0 M
-10
10
20
30
60
50
40
1.0 k
10 k
V
KA
= V
ref
I
K
= 10 mA
T
A
= 25
C
I
K
Output
Input
80
, OPEN LOOP
VOL
T
AGE GAIN (dB)
230
GND
Output
I
K
9.0
mF
8.25 k
15 k
I
K
= 10 mA
T
A
= 25
C
-55
0.01
100
10
1.0
0.1
T
A
, AMBIENT TEMPERATURE (5C)
75
-25
0
25
50
100
125
40
1.0 k
V
KA
, CATHODE VOLTAGE (V)
30
10
0
-32
-8.0
-16
20
0
-24
R2
V
ref
R1
I
K
Input
V
KA
Input
I
off
V
KA
= 36 V
V
ref
= 0 V
V
KA
V
ref
, REFERENCE INPUT
VOL
T
AGE (mV)
I of
f, OFF-ST
A
TE CA
THODE CURRENT
(nA)
I
K
= 10 mA
T
A
= 25
C
Figure 8. Change in Reference Input
Voltage versus Cathode Voltage
Figure 9. Off-State Cathode Current
versus Ambient Temperature
Figure 10. Dynamic Impedance
versus Frequency
Figure 11. Dynamic Impedance
versus Ambient Temperature
Figure 12. Open-Loop Voltage Gain
versus Frequency
Figure 13. Spectral Noise Density
VOL
A
TL431, A, B Series, NCV431A
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Input
Output
t, TIME (
ms)
Pulse
Generator
f = 100 kHz
0
8.0
4.0
20
0
16
2.0
3.0
12
0
1.0
5.0
Figure 14. Pulse Response
Figure 15. Stability Boundary Conditions
50
220 Output
GND
Input
Monitor
T
A
= 25
C
VOL
T
AGE SWING (V)
T
A
= 25
C
C
A
B
C
L
, LOAD CAPACITANCE
120
80
100
60
0
I K
, CA
THODE CURRENT
(mA)
140
1.0 nF
100
mF
1.0
mF
10
mF
Stable
Stable
40
20
10 nF
100 nF
A
B
D
Unstable
Area
Programmed
V
KA
(V)
A
B
C
D
V
ref
5.0
10
15
Figure 16. Test Circuit For Curve A
of Stability Boundary Conditions
Figure 17. Test Circuit For Curves B, C, And D
of Stability Boundary Conditions
V+
I
K
150
I
K
V+
150
C
L
10 k
C
L
Figure 18. Shunt Regulator
Figure 19. High Current Shunt Regulator
V+
V
out
R1
V+
V
out
R1
R2
R2
Vout + 1 )
R1
R2
V
ref
Vout + 1 )
R1
R2
V
ref
TYPICAL APPLICATIONS
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8
Figure 20. Output Control for a
Three-Terminal Fixed Regulator
Figure 21. Series Pass Regulator
V+
V
out
R1
R2
Out
In
MC7805
V+
V
out
R2
Common
R1
Vout + 1 )
R1
R2
V
ref
Vout min + Vref ) 5.0V
Vout + 1 )
R1
R2
V
ref
Vout min + Vref ) Vbe
Figure 22. Constant Current Source
Figure 23. Constant Current Sink
V+
R
CL
I
out
V+
R
S
I
Sink +
V
ref
R
S
Iout +
V
ref
R
CL
I
sink
Figure 24. TRIAC Crowbar
Figure 25. SRC Crowbar
V
out
V+
R2
V+
V
out
R1
R2
R1
V
out(trip) +
1
) R1
R2
V
ref
V
out(trip) +
1
) R1
R2
V
ref
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9
Figure 26. Voltage Monitor
Figure 27. Single-Supply Comparator with
Temperature-Compensated Threshold
V
th
= V
ref
V+
V
out
V
in
R1
R3
V+
V
out
R2
R4
l
L.E.D. indicator is `on' when V+ is between the
upper and lower limits.
Lower Limit
+ 1 ) R1
R2
V
ref
Upper Limit
+ 1 ) R3
R4
V
ref
V
in
V
out
< V
ref
V+
> V
ref
2.0 V
Figure 28. Linear Ohmmeter
Figure 29. Simple 400 mW Phono Amplifier
* Thermalloy
*
THM 6024
*
Heatsink on
*
LP Package
*
T
l
= 330 to 8.0
W
8.0
W
+
-
LM11
2.0 mA
25 V
25 V
-5.0 V
V
out
Range
V
1.0 M
W
V
100 k
W
V
V
1.0 k
W
R
X
5.0 M
1%
500 k
1%
50 k
1%
5.0 k
1%
47 k
Tone
0.05
mF
470
mF
Volume
1N5305
1.0
mF
T
I
360 k
330
56 k
10 k
25 k
38 V
+
10 k
W
10 k
Calibrate
Rx + Vout D
W
V
Range
TL431, A, B Series, NCV431A
http://onsemi.com
10
Figure 30. High Efficiency Step-Down Switching Converter
150
mH @ 2.0 A
1N5823
0.01
mF
+
470
mF
51 k
0.1
mF
+
2200
mF
4.7 k
V
in
= 10 V to 20 V
TIP115
MPSA20
1.0 k
4.7 k
4.7 k
10
2.2 k
100 k
V
out
= 5.0 V
I
out
= 1.0 A
Test
Conditions
Results
Line Regulation
V
in
= 10 V to 20 V, I
o
= 1.0 A
53 mV (1.1%)
Load Regulation
V
in
= 15 V, I
o
= 0 A to 1.0 A
25 mV (0.5%)
Output Ripple
V
in
= 10 V, I
o
= 1.0 A
50 mVpp
P.A.R.D.
Output Ripple
V
in
= 20 V, I
o
= 1.0 A
100 mVpp P.A.R.D.
Efficiency
V
in
= 15 V, I
o
= 1.0 A
82%
TL431, A, B Series, NCV431A
http://onsemi.com
11
APPLICATIONS INFORMATION
The TL431 is a programmable precision reference which
is used in a variety of ways. It serves as a reference voltage
in circuits where a non-standard reference voltage is
needed. Other uses include feedback control for driving an
optocoupler in power supplies, voltage monitor, constant
current source, constant current sink and series pass
regulator. In each of these applications, it is critical to
maintain stability of the device at various operating currents
and load capacitances. In some cases the circuit designer can
estimate the stabilization capacitance from the stability
boundary conditions curve provided in Figure 15. However,
these typical curves only provide stability information at
specific cathode voltages and at a specific load condition.
Additional information is needed to determine the
capacitance needed to optimize phase margin or allow for
process variation.
A simplified model of the TL431 is shown in Figure 31.
When tested for stability boundaries, the load resistance is
150
W. The model reference input consists of an input
transistor and a dc emitter resistance connected to the device
anode. A dependent current source, Gm, develops a current
whose amplitude is determined by the difference between
the 1.78 V internal reference voltage source and the input
transistor emitter voltage. A portion of Gm flows through
compensation capacitance, C
P2
. The voltage across C
P2
drives the output dependent current source, Go, which is
connected across the device cathode and anode.
Model component values are:
V
ref
= 1.78 V
Gm = 0.3 + 2.7 exp (-I
C
/26 mA)
where I
C
is the device cathode current and Gm is in mhos
Go = 1.25 (V
cp
2)
mmhos.
Resistor and capacitor typical values are shown on the
model. Process tolerances are
20% for resistors,
10% for
capacitors, and
40% for transconductances.
An examination of the device model reveals the location
of circuit poles and zeroes:
P1
+
1
2
p
R
GM
C
P1
+
1
2
p
* 1.0 M * 20 pF
+
7.96 kHz
P2
+
1
2
p
R
P2
C
P2
+
1
2
p
* 10 M * 0.265 pF
+
60 kHz
Z1
+
1
2
p
R
Z1
C
P1
+
1
2
p
* 15.9 k * 20 pF
+
500 kHz
In addition, there is an external circuit pole defined by the
load:
P
L
+
1
2
p
R
L
C
L
Also, the transfer dc voltage gain of the TL431 is:
G
+
G
M
R
GM
GoR
L
Example 1:
I
C
+
10 mA, R
L
+
230
W
, C
L
+
0. Define the transfer gain .
The DC gain is:
G
+
G
M
R
GM
GoR
L
+
(2.138)(1.0 M)(1.25
m
)(230)
+
615
+
56 dB
Loop gain
+
G
8.25 k
8.25 k
)
15 k
+
218
+
47 dB
The resulting transfer function Bode plot is shown in
Figure 32. The asymptotic plot may be expressed as the
following equation:
Av
+
615
1
)
jf
500 kHz
1
)
jf
8.0 kHz
1
)
jf
60 kHz
The Bode plot shows a unity gain crossover frequency of
approximately 600 kHz. The phase margin, calculated from
the equation, would be 55.9 degrees. This model matches the
Open-Loop Bode Plot of Figure 12. The total loop would
have a unity gain frequency of about 300 kHz with a phase
margin of about 44 degrees.
TL431, A, B Series, NCV431A
http://onsemi.com
12
Figure 31. Simplified TL431 Device Model
+
R
L
V
CC
-
C
L
15 k
9.0
mF
Input
8.25 k
3
Cathode
500 k
V
ref
1.78 V
R
ref
16
G
M
Anode
2
R
GM
1.0 M
Ref
1
Go
1.0
mmho
C
P2
0.265 pF
R
P2
10 M
R
Z1
15.9 k
C
P1
20 pF
f, FREQUENCY (Hz)
10
2
10
1
-20
30
20
60
0
A
v
, OPEN-LOOP
VOL
T
AGE GAIN (dB)
Figure 32. Example 1 Circuit Open Loop Gain Plot
TL431 OPEN-LOOP VOLTAGE GAIN VERSUS FREQUENCY
40
10
4
10
3
10
7
10
5
10
6
10
-10
50
Example 2.
I
C
= 7.5 mA, R
L
= 2.2 k
W, C
L
= 0.01
mF. Cathode tied to
reference input pin. An examination of the data sheet
stability boundary curve (Figure 15) shows that this value of
load capacitance and cathode current is on the boundary.
Define the transfer gain.
The DC gain is:
G
+
G
M
R
GM
GoR
L
+
(2.323)(1.0 M)(1.25
m
)(2200)
+
6389
+
76 dB
The resulting open loop Bode plot is shown in Figure 33.
The asymptotic plot may be expressed as the following
equation:
Av
+
615
1
)
jf
500 kHz
1
)
jf
8.0 kHz
1
)
jf
60 kHz
1
)
jf
7.2 kHz
Note that the transfer function now has an extra pole
formed by the load capacitance and load resistance.
Note that the crossover frequency in this case is about
250 kHz, having a phase margin of about -46 degrees.
Therefore, instability of this circuit is likely.
f, FREQUENCY (Hz)
10
2
10
1
-20
40
20
80
0
A
v
, OPEN-LOOP
GAIN (dB)
Figure 33. Example 2 Circuit Open Loop Gain Plot
TL431 OPEN-LOOP BODE PLOT WITH LOAD CAP
60
10
4
10
3
10
6
10
5
With three poles, this system is unstable. The only hope
for stabilizing this circuit is to add a zero. However, that can
only be done by adding a series resistance to the output
capacitance, which will reduce its effectiveness as a noise
filter. Therefore, practically, in reference voltage
applications, the best solution appears to be to use a smaller
value of capacitance in low noise applications or a very
large value to provide noise filtering and a dominant pole
rolloff of the system.
TL431, A, B Series, NCV431A
http://onsemi.com
13
ORDERING INFORMATION
Device
Operating Temperature Range
Package Code
Shipping Information
Tolerance
TL431ACD
SOIC-8
1.0%
TL431ACDG
SOIC-8
(Pb-Free)
1.0%
TL431BCD
SOIC-8
98 Units / Rail
0.4%
TL431BCDG
SOIC-8
(Pb-Free)
0.4%
TL431CD
SOIC-8
2.2%
TL431ACDR2
SOIC-8
1.0%
TL431ACDR2G
SOIC-8
(Pb-Free)
1.0%
TL431BCDR2
SOIC-8
0.4%
TL431BCDR2G
SOIC-8
(Pb-Free)
2500 Units / Tape & Reel
0.4%
TL431CDR2
SOIC-8
2.2%
TL431CDR2G
SOIC-8
(Pb-Free)
2.2%
TL431ACDMR2
Micro8
1.0%
TL431BCDMR2
Micro8
0.4%
TL431BCDMR2G
Micro8
(Pb-Free)
4000 Units / Tape & Reel
0.4%
TL431CDMR2
Micro8
2.2%
TL431CDMR2G
Micro8
(Pb-Free)
2.2%
TL431ACP
1.0%
TL431BCP
0
C to 70
C
PDIP-8
0.4%
TL431CP
0
C to 70
C
50 Units / Rail
2.2%
TL431CPG
PDIP-8
(Pb-Free)
2.2%
TL431ACLP
TO-92 (TO-226)
1.0%
TL431ACLPG
TO-92 (TO-226)
(Pb-Free)
1.0%
TL431BCLP
TO-92 (TO-226)
0.4%
TL431BCLPG
TO-92 (TO-226)
(Pb-Free)
2000 Units / Bag
0.4%
TL431CLP
TO-92 (TO-226)
2.2%
TL431CLPG
TO-92 (TO-226)
(Pb-Free)
2.2%
TL431ACLPRA
TO-92 (TO-226)
1.0%
TL431ACLPRAG
TO-92 (TO-226)
(Pb-Free)
1.0%
TL431BCLPRA
TO-92 (TO-226)
0.4%
TL431BCLPRAG
TO-92 (TO-226)
(Pb-Free)
0.4%
TL431CLPRA
TO-92 (TO-226)
2000 Units / Tape & Reel
2.2%
TL431CLPRAG
TO-92 (TO-226)
(Pb-Free)
2.2%
TL431ACLPRE
TO-92 (TO-226)
1.0%
TL431ACLPREG
TO-92 (TO-226)
(Pb-Free)
1.0%
TL431BCLPRE
TO-92 (TO-226)
0.4%
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
TL431, A, B Series, NCV431A
http://onsemi.com
14
ORDERING INFORMATION
Device
Tolerance
Shipping Information
Package Code
Operating Temperature Range
TL431BCLPREG
TO-92 (TO-226)
(Pb-Free)
2000 Units / Tape & Reel
0.4%
TL431ACLPRP
TO-92 (TO-226)
1.0%
TL431ACLPRPG
TO-92 (TO-226)
(Pb-Free)
1.0%
TL431BCLPRM
0
C to 70
C
TO-92 (TO-226)
0.4%
TL431BCLPRMG
TO-92 (TO-226)
(Pb-Free)
2000 Units / Fan-Fold
0.4%
TL431CLPRP
TO-92 (TO-226)
2.2%
TL431CLPRPG
TO-92 (TO-226)
(Pb-Free)
2.2%
TL431AID
SOIC-8
1.0%
TL431AIDG
SOIC-8
(Pb-Free)
1.0%
TL431BID
SOIC-8
0.4%
TL431BIDG
SOIC-8
(Pb-Free)
98 Units / Rail
0.4%
TL431ID
SOIC-8
2.2%
TL431IDG
SOIC-8
(Pb-Free)
2.2%
TL431AIDR2
SOIC-8
1.0%
TL431AIDR2G
SOIC-8
(Pb-Free)
1.0%
TL431BIDR2
SOIC-8
0.4%
TL431BIDR2G
SOIC-8
(Pb-Free)
2500 Units / Tape & Reel
0.4%
TL431IDR2
SOIC-8
2.2%
TL431IDR2G
SOIC-8
(Pb-Free)
2.2%
TL431AIDMR2
Micro8
1.0%
TL431BIDMR2
-40
C to 85
C
Micro8
0.4%
TL431BIDMR2G
-40
C to 85
C
Micro8
(Pb-Free)
4000 Units / Tape & Reel
0.4%
TL431IDMR2
Micro8
2.2%
TL431IDMR2G
Micro8
(Pb-Free)
2.2%
TL431AIP
PDIP-8
1.0%
TL431AIPG
PDIP-8
(Pb-Free)
50 Units / Rail
1.0%
TL431BIP
PDIP-8
50 Units / Rail
0.4%
TL431IP
PDIP-8
2.2%
TL431AILP
TO-92 (TO-226)
1.0%
TL431BILP
TO-92 (TO-226)
0.4%
TL431BILPG
TO-92 (TO-226)
(Pb-Free)
2000 Units / Box
0.4%
TL431ILP
TO-92 (TO-226)
2.2%
TL431ILPG
TO-92 (TO-226)
(Pb-Free)
2.2%
TL431AILPRA
TO-92 (TO-226)
1.0%
TL431AILPRAG
TO-92 (TO-226)
(Pb-Free)
2000 Units / Tape & Reel
1.0%
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
TL431, A, B Series, NCV431A
http://onsemi.com
15
ORDERING INFORMATION
Device
Tolerance
Shipping Information
Package Code
Operating Temperature Range
TL431BILPRA
TO-92 (TO-226)
0.4%
TL431BILPRAG
TO-92 (TO-226)
(Pb-Free)
2000 Units / Tape & Reel
0.4%
TL431ILPRA
TO-92 (TO-226)
2000 Units / Tape & Reel
2.2%
TL431ILPRAG
-40
C to 85
C
TO-92 (TO-226)
(Pb-Free)
2.2%
TL431AILPRM
1.0%
TL431AILPRP
TO-92 (TO-226)
2000 Units / Ammo Pack
1.0%
TL431ILPRP
(
)
2.2%
TL431BVD
SOIC-8
98 Units / Rail
0.4%
TL431BVDR2
SOIC-8
98 Units / Rail
0.4%
TL431BVDMR2
40
C to 125
C
Micro8
4000 Units / Tape & Reel
0.4%
TL431BVLP
-40
C to 125
C
TO-92 (TO-226)
2000 Units / Box
0.4%
TL431BVP
PDIP-8
50 Units / Rail
0.4%
NCV431AIDMR2
Micro8
4000 Units / Tape & Reel
1%
NCV431AIDR2
SOIC-8
2500 Units / Tape & Reel
1%
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SOIC-8
D SUFFIX
CASE 751
MARKING DIAGRAMS
Micro8
CASE 846A
TO-92 (TO-226)
CASE 29
PDIP-8
CASE 626
xx
AYW
1
8
xx
AWL
YYWW
1
8
1 2 3
xx
xx
= Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
xx
ALYW
1
8
TL431, A, B Series, NCV431A
http://onsemi.com
16
PACKAGE DIMENSIONS
TO-92 (TO-226)
LP SUFFIX
PLASTIC PACKAGE
CASE 29-11
ISSUE AL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
R
A
P
J
L
B
K
G
H
SECTION X-X
C
V
D
N
N
X X
SEATING
PLANE
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.175
0.205
4.45
5.20
B
0.170
0.210
4.32
5.33
C
0.125
0.165
3.18
4.19
D
0.016
0.021
0.407
0.533
G
0.045
0.055
1.15
1.39
H
0.095
0.105
2.42
2.66
J
0.015
0.020
0.39
0.50
K
0.500
---
12.70
---
L
0.250
---
6.35
---
N
0.080
0.105
2.04
2.66
P
---
0.100
---
2.54
R
0.115
---
2.93
---
V
0.135
---
3.43
---
1
PDIP-8
P SUFFIX
PLASTIC PACKAGE
CASE 626-05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1
4
5
8
F
NOTE 2
-A-
-B-
-T-
SEATING
PLANE
H
J
G
D
K
N
C
L
M
M
A
M
0.13 (0.005)
B
M
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.40
10.16
0.370
0.400
B
6.10
6.60
0.240
0.260
C
3.94
4.45
0.155
0.175
D
0.38
0.51
0.015
0.020
F
1.02
1.78
0.040
0.070
G
2.54 BSC
0.100 BSC
H
0.76
1.27
0.030
0.050
J
0.20
0.30
0.008
0.012
K
2.92
3.43
0.115
0.135
L
7.62 BSC
0.300 BSC
M
---
10
---
10
N
0.76
1.01
0.030
0.040
_
_
TL431, A, B Series, NCV431A
http://onsemi.com
17
PACKAGE DIMENSIONS
Micro8
DM SUFFIX
PLASTIC PACKAGE
CASE 846A-02
ISSUE F
S
B
M
0.08 (0.003)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
2.90
3.10
0.114
0.122
B
2.90
3.10
0.114
0.122
C
---
1.10
---
0.043
D
0.25
0.40
0.010
0.016
G
0.65 BSC
0.026 BSC
H
0.05
0.15
0.002
0.006
J
0.13
0.23
0.005
0.009
K
4.75
5.05
0.187
0.199
L
0.40
0.70
0.016
0.028
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
-B-
-A-
D
K
G
PIN 1 ID
8 PL
0.038 (0.0015)
-T-
SEATING
PLANE
C
H
J
L
8X
8X
6X
mm
inches
SCALE 8:1
1.04
0.041
0.38
0.015
5.28
0.208
4.24
0.167
3.20
0.126
0.65
0.0256
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
TL431, A, B Series, NCV431A
http://onsemi.com
18
SOIC-8
D SUFFIX
PLASTIC PACKAGE
CASE 751-07
ISSUE AE
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN
MAX
MIN
MAX
INCHES
4.80
5.00
0.189
0.197
MILLIMETERS
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.053
0.069
D
0.33
0.51
0.013
0.020
G
1.27 BSC
0.050 BSC
H
0.10
0.25
0.004
0.010
J
0.19
0.25
0.007
0.010
K
0.40
1.27
0.016
0.050
M
0
8
0
8
N
0.25
0.50
0.010
0.020
S
5.80
6.20
0.228
0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010)
Z
S
X
S
M
_
_
_
_
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