For Communications Equipment
Function
Message coding:
MH, MR, MMR, and MG3. The chip also supports
data transfers on the image and system buses and DMA
transfers on the image bus alone.
Coding conversion
The chip converts between all supported message
coding systems: MH, MR, MMR, and MG3.
Enlargement/reduction
These may be added to coding, decoding, code
conversion, and data transfer operations.
(1)
In the primary scan direction, the chip uses
multiplication on the change point address. The
scaling factor can be anywhere between approximately
0.1% and 200% in increments of approximately
0.1%. Integral multiplication is also available
beyond this
(2)
In the subscanning direction, the chip uses
decimation and replication. The scaling factor can
be anywhere between approximately 0.0015% and
200% in increments of approximately 0.0015%.
Integral multiplication is also available from 2 to
65,535.
White masks for both edges
These may be added to coding, decoding, code
conversion, and data transfer operations. They change
all pixels within the margins, specified in bit
increments, to white.
Decoding error processing
The chip offers a choice of replacing with the previous
line or a white line.
Applications
Facsimile equipment
Overview
The MN86063 is a high-speed LSI codec for compressing
and decompressing facsimile images. Features include
real-time printing to laser printers, built-in line memory,
enlargement and reduction, and code conversion.
Features
Pixels per line:
between 16 and 4864 bits, in word (16-bit) increments.
Processing time per line:
Individual pixels are processed within two system
clock cycles. For a machine cycle of 10 MHz,
processing the worst-case pattern for a 4096-bit line
takes no more than 1 ms.
Time-shared, multiplex processing
Support for time-shared, multiplex processing allows
image I/O, enlargement/reduction processing, and
coding/decoding to proceed concurrently for a group
of lines. Image bus DMA transfers can also proceed
concurrently with command processing.
Multiple channels
If lines consist of 2432 bits or fewer, commands can
be processed simultaneously on two channels using
time-sharing. These commands may be issued
asynchronously.
Bus configuration
There are separate system and image buses. The latter
features two independent master DMA channels; the
former, four slave DMA channel pins.
Image data I/O
Image data I/O can use either the image or system bus.
Byte conversion
When the system bus is 16 bits wide, the chip can swap
the upper and lower bytes of image or coded data. It
can also swap the MSB and LSB.
Memory management
The chip includes pointer management for the image
buffer connected to the image bus.
Machine cycle
The limit is 10 MHz. This means that the maximum
input clock is twice this, or 20 MHz.
MN86063
High-Speed CODEC LSI for Facsimile Images
MN86063
For Communications Equipment
Pin Assignment
V
SS3
V
DD3
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
V
SS4
V
DD4
TEST3
TEST2
TEST1
TEST0
RESET
IA0
IA1
IA2
IA3
IA4
IA5
IA6
IA7
IA8
IA9
IA10
IA11
IA12
IA13
IA14
IA15
V
DD2
V
SS2
DACK1
DACK0
DSTR0
DSTR1
IMLE
IMUE
DCMP0
HEX
INTR0
INTR1
INTR2
2SYSCLK
RD
WR
SYSCLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CS
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DCMP1
IREADY
IOW
IMW
IOR
IMR
DREQ0
DREQ1
IHACK
IHREQ
V
DD1
V
SS1
A0
A1
A2
A3
ACKD1
ACKD0
ACKC1
ACKC0
REQD1
REQD0
REQC1
REQC0
UBE
QFP100-P-1818
For Communications Equipment
MN86063
Pin Configuration
The MN86063 features two buses: the system bus, which is primarily used for transferring coded data to and from
a microprocessor and other components and the image bus, which is used for transferring image data to or from a
scanner, printer, or the like.
Pin Function Chart
The chip has a total of 100 pins: 39 for the system bus, 49 for the image bus, and 12 for testing, power supply, and
other purposes.
IA0 to 15
ID0 to 15
IHREQ
IHACK
IREADY
IMUE
IMLE
IMR
IMW
DSTR0
DSTR1
DREQ0
DREQ1
DACK0
DACK1
DCMP0
DCMP1
IOR
IOW
VDD0 to 3
VSS0 to 3
A0 to A3
D0 to D15
UBE
RD
WR
CS
HEX
RESET
REQC0
REQC1
REQD0
REQD1
ACKC0
ACKC1
ACKD0
ACKD1
2SYSCLK
SYSCLK
TEST0 to 3
INTR0 to 2
MN8606X
System bus pins
Image bus pins
MN86063
For Communications Equipment
35
A3
I
Address. Address bus for accessing internal registers
36
A2
37
A1
38
A0
9
D15
I/O
Data. Data bus for bidirectional transfers over system bus
10
D14
Tristate
11
D13
12
D12
13
D11
14
D10
15
D9
16
D8
17
D7
18
D6
19
D5
20
D4
21
D3
22
D2
23
D1
24
D0
26
UBE
I
Upper byte enable. This input pin specifies whether the data from pins
D15D8 is effective.
6
RD
I
Read. This input pin specifies a read from the specified register.
7
WR
I
Write. This input pin specifies a write to the specified register.
25
CS
I
Chip select. This input pin specifies access to a register.
1
HEX
I
Data bus width selection. This input pin specifies the width of the system
data bus: "0" for 16 bits; "1" for 8 bits.
100
RESET
I
Reset. This input pin resets the internal circuitry, clearing all registers.
2
INTR0
O
Interrupt request 0. This output pin indicates an interrupt request
Open
triggered by the cause given in interrupt register 0 (STIR0)
corrector
3
INTR1
O
Interrupt request 1. This output pin indicates an interrupt request
Open
triggered by the cause given in interrupt register 1 (STIR1)
corrector
4
INTR2
O
Interrupt request 2. This output pin indicates an interrupt request
Open
triggered by the cause given in DMA transfer interrupt register (DMIR).
corrector
27
REQC0
O
DMA transfer output request 0. This output pin indicates a request for
data output on DMA channel 0.
28
REQC1
O
DMA transfer output request 1. This output pin indicates a request for
data output on DMA channel 1.
System Bus
Pin No.
Symbol
I/O
Function Description
Pin Descriptions
For Communications Equipment
MN86063
29
REQD0
O
DMA transfer input request 0. This output pin indicates a request for data
input on DMA channel 0.
30
REQD1
O
DMA transfer input request 1. This output pin indicates a request for data
input on DMA channel 1.
31
ACKC0
I
DMA transfer output acknowledge 0. This input pin accepts the response
to a DMA transfer request with REQC0.
32
ACKC1
I
DMA transfer output acknowledge 0. This input pin accepts the response
to a DMA transfer request with REQC1.
33
ACKD0
I
DMA transfer input acknowledge 0. This input pin accepts the response
to a DMA transfer request with REQD0.
34
ACKD1
I
DMA transfer input acknowledge 0. This input pin accepts the response
to a DMA transfer request with REQD1.
5
2SYSCLK
I
2 system clock. This input pin accepts a clock signal with a frequency
twice that of the system clock.
8
SYSCLK
O
System clock. This output pin provides a clock signal with half the
frequency of 2SYSCLK.
System Bus (continued)
Pin No.
Symbol
I/O
Function Description
Pin Descriptions (continued)
60
IA15
O
Image address bus. These pins provide an address on the image data bus.
61
1A14
Tristate
62
IA13
63
IA12
64
IA11
65
IA10
66
IA9
67
IA8
68
IA7
69
IA6
70
IA5
71
IA4
72
IA3
73
IA2
74
IA1
75
IA0
Image Bus
Pin No.
Symbol
I/O
Function Description
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