www.docs.chipfind.ru
1
PS8744A 06/23/05
Features
Four Pairs of Differential Clocks
Low skew < 50ps
Low jitter < 50ps
Output Enable for all outputs
Outputs tristate control via SMBus
Power Management Control
Programmable PLL Bandwidth
PLL or Fanout operation
3.3V Operation
Packaging:
- 28-Pin SSOP (H) & 28-Pin TSSOP (L)
- Pb-Free and Green Option (HE and LE)
PI6C20400
Description
Pericom Semiconductors PI6C20400 is a high-speed, low-noise
differential clock buffer designed to be companion to PI6C410B.
The device distributes the differential SRC clock from PI6C410B
to four differential pairs of clock outputs either with or without
PLL. The clock outputs are controlled by input selection of
SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When
input of either SRC_STOP# or PWRDWN# is low, the output
clocks are Tristated. When PWRDWN# is low, the SDA and
SCLK inputs must be Tristated.
Block Diagram
1:4 Clock Driver for Intel
PCI Express Chipsets
Pin Configuration
V
DD_A
V
SS_A
I
REF
OE_INV
V
DD
OUT3
OUT3#
OE_3
OUT2
OUT2#
V
DD
PLL_BW#
SRC_STOP#
PWRDWN#
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V
DD
SRC
SCR#
V
SS
V
DD
OUT0
OUT0#
OE_0
OUT1
OUT1#
V
DD
PLL/BYPASS#
SCLK
SDA
OUT0
OUT0#
OUT0
OUT1#
OUT2
OUT2#
OUT3
OUT3#
DIV
Output
Control
SMBus
Controller
PLL
PLL_BW#
SRC
SRC#
PLL/BYPASS#
SCLK
SDA
OE_INV
OE_0 & OE_3
SRC_STOP#
PWRDWN#
2
PS8744A 06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Pin Descriptions
Pin Name
Type
Pin No
Description
SRC & SRC#
Input
2, 3
0.7V Differential SRC input from PI6C410 clock synthesizer
OE_0 & OE_3
Input
8, 21
3.3V LVTTL input for enabling outputs, active high.
OE_0 for OUT0 / OUT0#
OE_3 for OUT3 / OUT3#
OE_INV
Input
25
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins.
When 0 = same stage
When 1 = OE_0, OE_3, SRC_STOP#, PWRDWN# inverted.
OUT[0:3] & OUT[0:3]# Output
6, 7, 9, 10, 19, 20,
22, 23
0.7V Differential outputs
PLL/BYPASS#
Input
12
3.3V LVTTL input for selecting fan-out of PLL operation.
SCLK
Input
13
SMBus compatible SCLOCK input
SDA
I/O
14
SMBus compatible SDATA
IREF
Input
26
External resistor connection to set the differential output current
SRC_STOP#
Input
16
3.3V LVTTL input for SRC stop, active low
PLL_BW#
Input
17
3.3V LVTTL input for selecting the PLL bandwidth
PWRDWN#
Input
15
3.3V LVTTL input for Power Down operation, active low
V
DD
Power
1, 5, 11, 18, 24
3.3V Power Supply for Outputs
VSS
Ground
4
Ground for Outputs
VSS_A
Ground
27
Ground for PLL
VDD_A
Power
28
3.3V Power Supply for PLL
Serial Data Interface (SMBus)
PI6C20400 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit
address and read/write bit as shown below.
Address assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
1
1
0
0/1
Data Protocol
1 bit
7 bits
1
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Start
bit
Slave
Addr
R/W
Ack
Register
offset
Ack
Byte
Count
= N
Ack
Data
Byte 0
Ack
...
Data
Byte N
- 1
Ack
Stop
bit
Notes:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
3
PS8744A 06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Data Byte 0: Control Register
Bit
Descriptions
Type
Power Up Condition
Output(s) Affected
Source
Pin
0
Outputs Mode
0 = Divide by 2
1 = Normal
RW
1 = Normal
OUT[0:3], OUT[0:3]#
NA
1
PLL/BYPASS#
0 = Fanout
1 = PLL
RW
1 = PLL
OUT[0:3], OUT[0:3]#
NA
2
PLL Bandwidth
0 = High Bandwidth,
1 = Low Bandwidth
RW
1 = Low
OUT[0:3], OUT[0:3]#
NA
3
TBD
NA
4
TBD
NA
5
TBD
NA
6
SRC_STOP#
0 = Driven when stopped
1 = Tristate
RW
0 = Driven when stopped
OUT[0:3], OUT[0:3]#
7
PWRDWN#
0 = Driven when stopped
1 = Tristate
RW
0 = Driven when stopped
OUT[0:3], OUT[0:3]#
NA
Data Byte 1: Control Register
Bit
Descriptions
Type
Power Up Condition
Output(s) Affected
Source
Pin
0
1
OUTPUTS enable
1 = Enabled
0 = Disabled
RW
1 = Enabled
OUT0, OUT0#
NA
2
RW
1 = Enabled
OUT1, OUT1#
NA
3
4
5
OUTPUTS enable
1 = Enabled
0 = Disabled
RW
1 = Enabled
OUT2, OUT2#
NA
6
RW
1 = Enabled
OUT3, OUT3#
NA
7
4
PS8744A 06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Data Byte 2: Control Register
Bit
Descriptions
Type
Power Up Condition
Output(s) Affected
Source
Pin
0
1
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
RW
0 = Free running
OUT0, OUT0#
NA
2
RW
0 = Free running
OUT1, OUT1#
NA
3
4
5
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
RW
0 = Free running
OUT2, OUT2#
NA
6
RW
0 = Free running
OUT3, OUT3#
NA
7
Data Byte 3: Control Register
Bit
Descriptions
Type
Power Up Condition
Output(s) Affected
Source
Pin
0
TBD
RW
1
RW
2
RW
3
RW
4
RW
5
RW
6
RW
7
RW
Data Byte 4: Pericom ID Register
Bit
Descriptions
Type
Power Up Condition
Output(s) Affected
Pin
0
Pericom ID
R
0
NA
NA
1
R
0
NA
NA
2
R
0
NA
NA
3
R
0
NA
NA
4
R
0
NA
NA
5
R
1
NA
NA
6
R
0
NA
NA
7
R
0
NA
NA
5
PS8744A 06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
PWRDWN#
OUT
OUT#
Tdrive_PwrDwn#
<300us, >200mV
Tstable
<1ms
Functionality
PWRDWN#
OUT
OUT#
SRC_Stop#
OUT
OUT#
1
Normal
Normal
1
Normal
Normal
0
I
REF
2 or Float
Low
0
I
REF
6 or Float
Low
Power Down (PWRDWN# assertion)
Figure 1. Power down sequence
PWRDWN#
OUT#
OUT
Power Down (PWRDWN# De-assertion)
Figure 2. Power down de-assert sequence
PDF 
ZIP