1
PS8590C 09/22/04
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PI6C2972
Description
The PI6C2972 are 3.3V compatible, PLL based clock driver devices
targeted for high-performance CISC or RISC processor based sys-
tems. With output frequencies of up to 125 MHz and skews of 550ps
the PI6C2972 are ideally suited for most synchronous systems. The
devices offer twelve low skew outputs plus a feedback and sync
output for added flexibility and ease of system implementation.
The PI6C2972 features an extensive level of frequency programma-
bility between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of 1:1,
2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be
realized by pulsing low one clock edge prior to the coincident edges
of the Qa and Qc outputs. The Sync output will indicate when the
coincident rising edges of the above relationships will occur. The
PowerOn Reset ensures proper programming if the frequency
select pins are set at power up. If the fselFB2 pin is held high, it may
be necessary to apply a reset after powerup to ensure synchroni-
zation between the QFB output and the other outputs. The internal
poweron reset is designed to provide this function, but with
powerup conditions being dependent, it is difficult to guarantee.
All other conditions of the fsel pins will automatically synchronize
during PLL lock acquisition.
The PI6C2972 offers a very flexible output enable/disable scheme.
Note that all of the control inputs on the PI6C2972 have internal pull
up resistors.
The PI6C2972 is fully 3.3V compatible and requires no external loop
filter components. All inputs accept LVCMOS/LVTTL compatible
levels while the outputs provide LVCMOS levels with the capability
to drive 50-ohm transmission lines. For series terminated lines each
PI6C2972 output can drive two 50-ohm lines in parallel thus effec-
tively doubling the fanout of the device.
Features
Fully Integrated PLL
Output Frequency up to 125 MHz
Compatible with PowerPC and Pentium Microprocessors
3.3V V
CC
+ 100ps Typical CycletoCycle Jitter
Packaging (Pb-free & Green available):
- 52-pin LQFP (FC)
Low Voltage PLL Clock Driver
Pin Configuration
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
1 2 3 4 5 6 7 8 9 10 11 12 13
39 38 37 36 35 34 33 32 31 30 29 28 27
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GND0
VCO_Sel
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GND0
Inv_Clk
GNDO
Qb0
VCCO
Qb1
GND0
Qb2
VCCO
Qb3
Ext_FB
GNDO
QFB
VCCI
fselFB0
GND1
MR/OE
Frz_Clk
Frz_Data
fselFB2
PLL_EN
Ref_Sel
TClk_Sel
TClk0
TClk1
xtal1
xtal2
VCCA
2
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PI6C2972
Low Voltage PLL Clock Driver
Block Diagram
VCO
PHASE
DETECTOR
V
Qa1
Qa0
Qa3
Qa2
Qb3
Qb2
Qb1
Qb0
Qc3
Qc2
Qc1
Qc0
QSync
QFB
V
V
V
Sync
Frz
2
2
2
2
2
4, 6, 8, 12
4, 6, 8, 10
2, 4, 6, 8
4, 6, 8, 10
Sync Pulse
Data Generator
0
D
Q
D
Q
1
Sync
Frz
Sync
Frz
LPF
0
1
0
1
TCLK1
TCLK_Sel
Ext_FB
TCLK0
PLL_En
REF_Sel
VC0_Sel
V
D
Q
fsela0:1
fselb0:1
fselc0:1
fselFBO:1
Frz_Clk
Frz_Data
Inv_Clk
MR/OE
fselFB2
POWER-ON
RESET
Output Disable
Circuitry
V
12
V
D
Q
V
D
Q
D
Q
Sync
Frz
Sync
Frz
xtal_1
xtal_2
V
3
PS8590C 09/22/04
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PI6C2972
Low Voltage PLL Clock Driver
Function Table 1
1
a
l
e
s
f
0
a
l
e
s
f
a
Q
1
b
l
e
s
f
0
b
l
e
s
f
b
Q
1
c
l
e
s
f
0
c
l
e
s
f
c
Q
0
0
1
1
0
1
0
1
4
6
8
2
1
0
0
1
1
0
1
0
1
4
6
8
0
1
0
0
1
1
0
1
0
1
2
4
6
8
2
B
F
l
e
s
f
1
B
F
l
e
s
f
0
B
F
l
e
s
f
B
F
Q
0
0
0
0
0
0
1
1
0
1
0
1
4
6
8
0
1
1
1
1
1
0
0
1
1
0
1
0
1
8
2
1
6
1
0
2
n
i
P
l
o
r
t
n
o
C
'
0
'
c
i
g
o
L
'
1
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c
i
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o
L
l
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S
_
O
C
V
l
e
S
_
f
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R
l
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S
_
K
L
C
T
n
E
_
L
L
P
E
O
/
R
M
K
L
C
_
v
n
I
2
/
O
C
V
K
L
C
T
0
K
L
C
T
L
L
P
s
s
a
p
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B
Z
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H
t
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p
t
u
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/t
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s
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R
r
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t
s
a
M
3
c
Q
,
2
c
Q
d
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t
r
e
v
n
I
-
n
o
N
O
C
V
l
a
t
X
1
K
L
C
T
L
L
P
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l
b
a
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E
s
t
u
p
t
u
O
e
l
b
a
n
E
3
c
Q
,
2
c
Q
d
e
t
r
e
v
n
I
Function Table 2
Function Table 3
s
r
e
t
e
m
a
r
a
P
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u
l
a
V
t
u
C
l
a
t
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C
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A
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a
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c
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a
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e
R
l
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ll
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r
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l
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.
q
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r
F
C
5
2
@
m
p
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0
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1
y
ti
li
b
a
t
S
.
p
m
e
T
.
q
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r
F
)
C
0
7
o
t
0
(
m
p
p
5
7
1
e
g
n
a
R
g
n
it
a
r
e
p
O
C
0
7
o
t
0
e
c
n
a
ti
c
a
p
a
C
t
n
u
h
S
F
p
7
<
R
S
E
m
h
O
-
0
4
<
l
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v
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5
g
n
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g
A
)
s
r
a
e
y
3
t
s
ri
F
(
r
a
e
Y
/
m
p
p
5
Crystal Recommendations
4
PS8590C 09/22/04
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PI6C2972
Low Voltage PLL Clock Driver
1:1 Mode
2:1 Mode
3:1 Mode
3:2 Mode
4:1 Mode
4:3 Mode
1:6 Mode
fVCO
Qa
Qc
Sync
Qa
Qc
Sync
Qc( 2)
Qa( 6)
Sync
Qa( 4)
Qc( 6)
Sync
Qc( 2)
Qa( 8)
Sync
Qa( 6)
Qc( 8)
Sync
Qa( 12)
Qc( 2)
Sync
Timing Diagrams
5
PS8590C 09/22/04
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PI6C2972
Low Voltage PLL Clock Driver
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2
Notes:
1. V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when
the "High" input is within the V
CMR
range and the input lies within the V
PP
specification.
2. The PI6C2972 outputs can drive series or parallel terminated 50 Ohm (or 50 Ohm to V
CC
/2) transmission lines on the
incident edge.
3. Inputs have pullup/pulldown resistors which affect input current.
4. Special thermal handling may be required in some configurations.
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1
C
*Absolute maximum continuous ratings are those values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute-maximum-rated conditions is not implied.
DC Characteristics (T
A
= 0C to 70C, V
CC
= 3.3V 5%)
(4)
Absolute Maximum Ratings
6
PS8590C 09/22/04
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PI6C2972
Low Voltage PLL Clock Driver
Notes:
7. 50 Ohm transmission line terminated into V
CC
/2
8. tpd is specified for a 50 MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/
longer input reference periods. The tpd does not include jitter.
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z
H
M
PLL Input Reference Characteristic (T
A
= 0C to 70C)
Notes:
5. Maximum input reference frequency is limited by the VCO lock range and the feedback divider or 100 MHz,
minimum input reference frequency is limited by the VCO lock range and the feedback divider.
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AC Characteristics (T
A
= 0C to 70C, V
CC
= 3.3V 5%)
7
PS8590C 09/22/04
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PI6C2972
Low Voltage PLL Clock Driver
Packaging Mechanical: 52-Pin LQFP (FC)
D0D3 are the control bits for Qa0Qa3, respectively
D4D7 are the control bits for Qb0Qb3, respectively
D8D10 are the control bits for Qc1Qc3, respectively
D11 is the control bit for QSync
Freeze Data Input Protocol
t
r
a
t
S
ti
B
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
0
1
D
1
1
D
Seating Plane
0.65 BSC
.026
0.22
0.38
.009
.015
1.60
.063
1.35
1.45
.053
.057
0.05
0.15
.002
.006
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
12.00 BSC
.394
Square
10.00 BSC
.472
Square
GAUGE PLANE
1.00 REF
.039
0.45
0.75
.018
.030
0.09
0.20
.004
.008
0.25 mm
Max.
0.10
.004
0
7
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Ordering Information
Ordering Code
Package Code
Package Type
PI6C2972FC
FC
52-pin LQFP
PI6C2972FCE
FC
Pb-free & Green, 52-pin LQFP
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