1
PS8449A 10/09/00
Features
PI6C3Q99X family provides following products:
PI6C3Q991: 32-pin PLCC version
PI6C3Q993: 28-pin QSOP version
Inputs are 5V I/O Tolerant
4 pairs of programmable skew outputs
Low skew: 200ps same pair; 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75 MHz to 85 MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: < 200ps peak-to-peak
Industrial temperature range
Pin-to-pin compatible with IDT QS5V991 and QS5V993
Available in 32-pin PLCC and 28-pin QSOP
Description
The PI6C3Q99X family is a high fanout 3.3V PLL-based clock driver
intended for high performance computing and data-communica-
tions applications. A key feature of the programmable skew is the
ability of outputs to lead or lag the REF input signal. The PI6C3Q991
has 8 programmable skew outputs in 4 banks of 2, while the
PI6C3Q993 has 6 programmable skew outputs and 2 zero skew
outputs. Skew is controlled by 3-level input signals that may be hard-
wired to appropriate HIGH-MID-LOW levels.
When the GND/sOE pin is held low, all the outputs are synchro-
nously enabled. However, if GND/sOE is held high, all the outputs
except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when
the V
CCQ
/PE is held high, all the outputs are synchronized with the
positive edge of the REF clock input. When V
CCQ
/PE is held low,
all the outputs are synchronized with the negative edge of REF. Both
devices have LVTTL outputs with 12mA balanced drive outputs.
Pin Configurations
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock
REF
VCCQ
FS
3F0
3F1
VCCQ/PE
VCCN
4Q1
4Q0
GND
3Q1
3Q0
VCCN
FB
GND
TEST
2F1
2F0
GND/sOE
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
2Q0
2Q1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2F0
GND/sOE
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
3F1
4F0
4F1
VCCQ/PE
VCCN
4Q1
4Q0
GND
GND
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3Q1
3Q0
V
CCN
FB
V
CCN
2Q1
2Q0
3Q0
FS
V
CCQ
REF
GND
TEST
2F1
4 3 2 1 32 31 30
14 15 16 17 18 19 20
PI6C3Q993
PI6C3Q991
28-Pin
Q
32-Pin
J
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PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver SuperClock
2
PS8449A 10/09/00
Pin Descriptions
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Note:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] =LL functioning as an output disable control for
individual output banks. Skew selections (see Table 3) remain in effect unless nF[1:0] = LL.
Logic Block Diagrams
PI6C3Q991
Skew
Select
3
3
3
1F1:0
1Q0
1Q1
Skew
Select
3
3
2F1:0
2Q0
2Q1
Skew
Select
3
3
3F1:0
3Q0
3Q1
Skew
Select
3
3
4F1:0
4Q0
4Q1
GND/sOE
REF
PLL
V
CCQ
/PE
FB
FS
PI6C3Q993
Skew
Select
3
3
3
1F1:0
1Q0
1Q1
Skew
Select
3
3
2F1:0
2Q0
2Q1
Skew
Select
3
3
3F1:0
3Q0
3Q1
4Q0
4Q1
GND/sOE
REF
PLL
V
CCQ
/PE
FB
FS
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock
3
PS8449A 10/09/00
Programmable Skew
Output skew with respect to the REF input is adjustable to compen-
sate for PCB trace delays, backplane propagation delays or to
accommodate requirements for special timing relationships between
clocked components. Skew is selectable as a multiple of a time unit
t
U
which is of the order of a nanosecond (see Table 2). There are 9
skew configurations available for each output pair. These configu-
rations are choosen by the nF1:0 control pins. In order to minimize
the number of control pins, 3-level inputs (HIGH-MID-LOW) are
used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew
is not a requirement, the control pins can be left open for the zero skew
default setting. The Skew Selection Table (Table 3) shows how to
select specific skew taps by using the nF1:0 control pins.
External Feedback
By providing external feedback, the PI6C3Q99X family gives users
flexibility with regard to skew adjustment. The FB signal is compared
with the input REF signal at the phase detector in order to drive the
VCO. Phase differences cause the VCO of the PLL to adjust upwards
or downwards accordingly. An internal loop filter moderates the
response of the VCO to the phase detector. The loop filter transfer
function has been chosen to provide minimal jitter (or frequency
variation) while still providing accurate responses to input fre-
quency changes.
W
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Table 2. PLL Programmable Skew Range and Resolution Table
Notes:
1. The device may be operated outside recommended frequency ranges without damage, but functional
operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the
PLL to operate in its sweet spot where jitter is lowest.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator.
The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their
undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the
output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO
frequency when the part is configured for a frequency multiplication by using a divided output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used
for feedback, then adjustment range will be greater. For example if a 4t
U
skewed output is used for feedback,
all other outputs will be skewed 4t
U
in addition to whatever skew value is programmed for those outputs.
Max adjustment range applies to output pairs 3 and 4 where 6 t
U
skew adjustment is possible and at the
lowest F
NOM
value.
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PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver SuperClock
4
PS8449A 10/09/00
0
:
1
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2
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Table 3. Skew Selection Table for Output Pairs
Notes:
1. Programmable skew on pair #4 is not applicable
for the PI6C993.
2. LL disables outputs if TEST = MID and GND/
sOE = HIGH.
3. When pair #4 is set to HH (inverted), GND/sOE
disables pair #4 HIGH when V
CCQ
/PE = HIGH,
GND/sOE disables pair #4 LOW when V
CCQ
/
PE = LOW
Supply Voltage to ground ........................................................0.5V to 7.0V
DC input Voltage V
I ....................................................................
0.5V to V
CC
+ 0.5V
Maximum Power Dissipation at T
A
= 85C, PLCC .........................0.80 watts
QSOP ....................... 0.66 watts
TSTG Storage temperature ....................................................65C to 150C
Table 4. Absolute Maximum Ratings
Table 5. Recommended Operating Range
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C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the
device at these or any other conditions above those listed in
the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock
5
PS8449A 10/09/00
l
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C
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2
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3
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0
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C
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3
.
0
+
2
/
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V
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I
V
=
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C
,
D
N
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r
o
V
C
C
.
x
a
M
=
5
A
I
3
t
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rr
u
C
C
D
t
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p
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3
)
0
:
1
F
n
,
S
F
,
T
S
E
T
(
V
N
I
V
=
C
C
V
N
I
V
=
C
C
2
/
V
N
I
D
N
G
=
l
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v
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L
H
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I
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l
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W
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0
0
2
0
5
0
0
2
I
U
P
t
n
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rr
u
C
p
U
-l
l
u
P
t
u
p
n
I
V
(
Q
C
C
)
E
P
/
V
C
C
V
,.
x
a
M
=
N
I
D
N
G
=
0
0
1
I
D
P
t
n
e
rr
u
C
n
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o
D
-l
l
u
P
t
u
p
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I
)
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O
s/
D
N
G
(
V
C
C
V
,.
x
a
M
=
N
I
V
=
C
C
0
0
1
V
H
O
e
g
a
tl
o
V
H
G
I
H
t
u
p
t
u
O
V
C
C
I
,.
n
i
M
=
H
O =
A
m
2
1
2
.
2
V
V
L
O
e
g
a
tl
o
V
W
O
L
t
u
p
t
u
O
V
C
C
I
,.
n
i
M
=
L
O =
A
m
2
1
5
5
.
0
Table 6. DC Characteristics Over Operating Range
Note:
1. These inputs are normally wired to V
CC
, GND, or unconnected. Internal termination resistors bias unconnected inputs
to V
CC
/2. If these inputs are switched, the function and timing of the outputs may glitched, and the PLL may require
an additional t
LOCK
time before all datasheet limits are achieved.
l
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=
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,.
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=
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V
C
C
V
,.
x
a
M
=
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V
0
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3
=
0
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1
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3
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(
V
C
C
C
,.
x
a
M
=
L
F
p
0
=
5
5
0
9
z
H
M
/
A
I
C
t
n
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rr
u
C
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l
p
p
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w
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P
l
a
t
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T
)
1
(
V
C
C
F
,
V
3
.
3
=
F
E
R
C
,z
H
M
0
2
=
L
F
p
0
6
1
=
)
2
(
9
2
A
m
I
C
t
n
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rr
u
C
y
l
p
p
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w
o
P
l
a
t
o
T
)
1
(
V
C
C
F
,
V
3
.
3
=
F
E
R
C
,z
H
M
3
3
=
L
F
p
0
6
1
=
)
2
(
2
4
I
C
t
n
e
rr
u
C
y
l
p
p
u
S
r
e
w
o
P
l
a
t
o
T
)
1
(
V
C
C
F
,
V
3
.
3
=
F
E
R
C
,z
H
M
6
6
=
L
F
p
0
6
1
=
)
2
(
6
7
Table 7. Power Supply Characteristics
Notes:
1. Guaranteed by characterization but not production tested.
2. For 8 outputs each loaded with 20pF.
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver SuperClock
6
PS8449A 10/09/00
Output
V
CC
150
150
20pF
1ns
1ns
3.0V
2.0V
Vth=1.5V
0.8V
0V
LVTTL Input Test Waveform
t
ORISE
t
PWH
t
PWL
t
OFALL
2.0V
0.8V
LVTTL Output Waveform
P
O
S
Q
C
C
L
P
s
ti
n
U
.
p
y
T
.
x
a
M
.
p
y
T
.
x
a
M
C
N
I
4
6
5
7
F
p
Table 8. Capacitance
(T
A
= 25C, f = 1 MHz, V
IN
= 0V)
AC Test Loads and Waveforms
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock
7
PS8449A 10/09/00
n
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p
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2
-
1
9
9
Q
3
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3
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Q
x
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c
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2
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1
(
5
0
.
0
0
2
.
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1
.
0
5
2
.
0
1
.
0
5
2
.
0
s
n
t
0
W
E
K
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C
)
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u
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ll
a
(
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k
s
t
u
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L
F
p
0
=
)
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,
1
(
1
.
0
5
2
.
0
5
2
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0
5
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0
3
.
0
5
7
.
0
t
1
W
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f
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r(
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2
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)
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r(
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3
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3
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V
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it
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m
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it
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v
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3
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L
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%
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5
m
o
rf
n
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it
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1
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1
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5
.
2
0
.
3
5
.
3
t
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S
I
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e
m
it
e
si
r
t
u
p
t
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(
5
1
.
0
0
.
1
8
.
1
5
1
.
0
0
.
1
8
.
1
5
1
.
0
5
.
1
5
.
2
t
L
L
A
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m
it
ll
a
f
t
u
p
t
u
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)
1
(
5
1
.
0
0
.
1
8
.
1
5
1
.
0
0
.
1
8
.
1
5
1
.
0
5
.
1
5
.
2
t
K
C
O
L
e
m
it
k
c
o
l
L
L
P
)
7
,
1
(
5
.
0
5
.
0
5
.
0
s
m
t
R
J
r
e
tt
ij
t
u
p
t
u
o
el
c
y
c
-
o
t
-
el
c
y
C
)
1
(
S
M
R
5
2
0
4
0
4
s
p
k
a
e
p
-
o
t
-
k
a
e
P
0
0
2
0
0
2
0
0
2
Table 9. Switching Characteristics Over Operating Range
Notes:
1. All timing tolerances apply for F NOM
25MHz. Guaranteed by design and characterization, not subject to 100%
production testing.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t
U
delay
has been selected when all are loaded with the specified load.
3. t
SKEWPR
is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t
U
.
4. t
SKEW0
is the skew between outputs when they are selected for 0t
U
.
5. There are 3 classes of outputs: Nominal (multiple of t
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH),
and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
6. t DEV is the output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient
temperature, air flow, etc.)
7. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is
stable and within normal operating limits. This parameter is measured from the application of a new signal or
frequency at REF or FB until t
PD
is within specified limits.
8. t
PD
is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
9. Measured at 2.0V.
10. Measured at 0.8V.
11. Refer to Table12 for more detail.
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver SuperClock
8
PS8449A 10/09/00
t
REF
t
RPWH
t
ODCV
t
SKEWPR
t
SKEW0, 1
t
SKEW3,4
t
SKEW3,4
t
SKEW3,4
t
SKEW2,4
t
SKEW1,3,4
t
SKEWPR
t
SKEW0, 1
t
PD
t
ODCV
t
RPWL
t
JR
REF
FB
Q
Other Q
Inverted Q
REF Divided by 2
REF Divided by 4
t
SKEW2
t
SKEW2
l
o
b
m
y
S
n
o
it
p
i
r
c
s
e
D
.
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P
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d
t
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0
1
0
9
%
Table 12. Input Timing Requirements
Notes:
1. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by D
H
is
less than t
PWC
limit, t
PWC
limit applies.
AC Timing Diagram
Notes:
V
CCQ
/PE: The AC timing diagram above applies to V
CCQ
/PE=V
CC
. For V
CCQ
/PE=GND, the negative edge of FB aligns with the negative edge of REF,
divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected when all are
loaded with 20pF and terminated with 75Ohm to V
CC
/2.
t
SKEWPR
: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t
U
.
t
SKEW0
:
The skew between outputs when they are selected for 0t U.
t
DEV
:
The output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.)
t
ODCV
:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
SKEW2
and t
SKEW4
specifications.
t
LOCK
:
The time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
t
PWH
is measured at 2.0V.
t
PWL
is measured at 0.8V.
t
ORISE
and t
OFALL
are measured between 0.8V and 2.0V.
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock
9
PS8449A 10/09/00
32-Pin PLCC Package Diagram
.386
.394
.053
.069
.004
.010
SEATING
PLANE
.025
BSC
.007
.010
.228
.244
0.150
0.157
1
28
.016
.050
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
0.635
9.804
10.009
1.35
1.75
5.79
6.19
0.41
1.27
0.101
0.254
.008
.012
0.203
0.305
3.81
3.99
0.178
0.254
.033
0.84
.015 x 45
REF
28-Pin QSOP Package Diagram
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver SuperClock
10
PS8449A 10/09/00
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
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Ordering Information
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