1
PS8639 10/18/02
Product Description
PI6CV857B PLL clock device is developed for registered DDR DIMM
applications This PLL Clock Buffer is designed for 2.5 V
DDQ
and 2.5V
AV
DD
operation and differential data input and output levels.
The device is a zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9],
Y[0:9]) and one differential pair feedback clock outputs
(FBOUT,FBOUT) . The clock outputs are controlled by the input
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V
LVCMOS input (PWRDWN) and the Analog Power input (AV
DD
).
When input PWRDWN is low while power is applied, the input
receivers are disabled, the PLL is turned off and the differential clock
outputs are 3-stated. When the AV
DD
is strapped low, the PLL is
turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
will enter a low power mode. An input frequency detection circuit will
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
The PLL in the PI6CV857B clock driver uses the input clocks (CLK,
CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor-
mance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]).
The PI6CV857B is also able to track Spread Spectrum Clocking for
reduced EMI.
VD D Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
35
36
34
33
32
31
30
29
28
27
26
25
F B O U T
G N D
G N D
G N D
F B I N
F B I N
P W R D W N
G N D
G N D
Y 9
Y 8
Y 8
F B O U T
Y 7
Y 7
Y 6
Y 6
Y 5
Y 5
Y 9
G N D
G N D
G N D
Y 0
Y 0
Y 1
Y 1
VD D Q
VD D Q
VD D Q
VD D Q
VD D Q
VD D Q
VD D Q
VD D Q
G N D
C L K
C L K
Y 2
Y 2
G N D
Y 3
Y 3
Y 4
Y 4
AG N D
AV D D
Product Features
Operating Frequency up to 200 MHz and exceeds PC2700
RDIMM specification
Distributes one differential clock input pair to ten differential
clock output pairs.
Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
Input PWRDWN: LVCMOS
Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input.
Operates at AV
DD
= 2.5V for core circuit and internal PLL,
and V
DDQ
= 2.5V for differential output drivers
Available Packages: Plastic 48-pin TSSOP
Block Diagram/Pin Configuration
PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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Y0
Y0
Y1
PWRDWN
AVDD
FBIN
FBIN
CLK
CLK
PLL
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
Powerdown
and Test
Logic
48-Pin
A
2
PS8639 10/18/02
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Function Table
s
t
u
p
n
I
s
t
u
p
t
u
O
L
L
P
V
A
D
D
N
W
D
R
W
P
K
L
C
K
L
C
Y
Y
T
U
O
B
F
T
U
O
B
F
D
N
G
H
L
H
L
H
L
H
f
f
o
/
d
e
s
s
a
p
y
B
D
N
G
H
H
L
H
L
H
L
f
f
o
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d
e
s
s
a
p
y
B
X
L
L
H
Z
Z
Z
Z
f
f
o
X
L
H
L
Z
Z
Z
Z
f
f
o
)
m
o
n
(
V
5
.
2
H
L
H
L
H
L
H
n
o
)
m
o
n
(
V
5
.
2
H
H
L
H
L
H
L
n
o
)
m
o
n
(
V
5
.
2
X
z
H
M
0
2
<
)
1
(
Z
Z
Z
Z
f
f
o
Notes: For testing and power saving purposes, PI6CV857B will power down if the frequency of the reference inputs CLK, CLK is
well below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CV857B will
be powered down when the CLK,CLK stop running.
Z = High impedance
X = Don't care
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6
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Pinout Table
3
PS8639 10/18/02
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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)
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7
C
DC Specifications
Recommended Operating Conditions
Absolute Maximum Ratings
(Over operating free-air temperature range)
Note: Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
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4
PS8639 10/18/02
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
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=
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7
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D
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Note:
4. The maximum power-down clock frequency is below 20 MHz.
5. Guaranteed by design, but not production tested.
Electrical Characteristics
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the
other timing parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
Timing Requirements
(Over recommended operating free-air temperature)
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5
PS8639 10/18/02
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PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
AC Specifications
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 )
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Notes:
1. Static Phase offset does not include Jitter.
2. The slew rate is determined from the IBIS model with test load shown in Figure1.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
6
PS8639 10/18/02
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PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Figure 2. Output Load Test Circuit
Figure 1. IBIS Model Output Load
VDDQ/2
VDDQ/2
Z=60
C=14pF
R=120
Z=60
GND
GND
R=1M
PROBE
PI6CV857L
R=1M
C=14pF
C=1pF
C=1pF
V
DD
PI6CV857
R=60
V
CLK
R=60
V
CLK
V
DD
/2
7
PS8639 10/18/02
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PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Figure 3. Cycle-to-Cycle Jitter
Figure 4. Static Phase Offset
Figure 5. Output Skew
F B I N
F B I N
C K
C K
t
( )
n
t
( )
n+1
t
=
1
n = N
t
( ) n
N
(N is a large number of samples)
t
jit(cc)
=
t
cycle n
-
t
cycle n+1
t
cycle n+1
t
cycle n
Y x , F B O U T
Y x , F B O U T
t
sk(o)
Y x
Y x
Y x , F B O U T
Y x , F B O U T
8
PS8639 10/18/02
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PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Figure 6. Period Jitter
Figure 7. Half-Period Jitter
Figure 8. Input and Output Slew Rates
Clock Inputs
and Outputs
V
ID
t
sl(i),
t
sl(o)
8 0 %
2 0 %
t
sl(i),
t
sl(o)
8 0 %
2 0 %
Y x , F B O U T
Y x , F B O U T
Y x , F B O U T
Y x , F B O U T
t
cycle n
f
O
1
t
jit(per)
=
t
cycle n
f
O
1
Yx, FBOUT
Yx, FBOUT
t
half period n
t
n+1
half period
f
O
1
t
jit(hper)
=
t
half period n
2*f
O
1
9
PS8639 10/18/02
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PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
Packaging Mechanical: 48-Pin TSSOP
.236
.244
.488
.496
.002
.006
SEATING PLANE
.007
.010
.0197
BSC
.004
.008
.319
1
48
12.4
12.6
6.0
6.2
0.50
0.17
0.27
8.1
0.05
0.15
0.09
0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.018
.030
0.45
0.75
.047
1.20 Max
BSC
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Ordering Information
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ZIP