1
PS8102A 10/07/98
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16-Bit Bus Transceiver and Register
with 3-STATE Outputs
PI74ALVCH16646
Product Features
PI74ALVCH16646 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at 40C to +85C
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced in the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16646 is a 16-bit bus transceiver and register
designed for 2.3V to 3.6V V
CC
operation. It can be used as two
8-bit transceivers or one 16-bit transceiver. Data on the A or B bus
is clocked into the registers on the low-to-high transition of the
appropriate Clock (CLKAB or CLKBA) input. Four fundamental
bus-management functions can be performed.
Output Enable (OE) and Direction Control (DIR) inputs are provided
to control the transceiver functions. In the transceiver mode, data
present at the high-impedance port may be stored in either register
or in both. The Select Control (SAB and SBA) inputs can multiplex
stored and real-time (transparent mode) data. Circuitry used for
Select Control eliminates the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-time
data. DIR determines which bus receives data when OE is LOW.
In the isolation mode (OE HIGH), A data may be stored in one
register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of the
two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
2
PS8102A 10/07/98
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PI74ALVCH16646
16-Bit Bus Transceiver and Register
with 3-STATE Outputs
1
DIR
1
1
CLKAB
2
1
SAB
3
GND
4
1
A
1
5
1
A
2
6
V
CC
7
1
A
3
8
1
A
4
9
1
A
5
10
GND
11
1
A
6
12
1
A
7
13
1
A
8
14
2
A
1
15
2
A
2
16
2
A
3
17
GND
18
2
A
4
19
2
A
5
20
2
A
6
21
V
CC
22
2
A
7
23
2
A
8
24
1
OE
56
1
CLKBA
55
1
SBA
54
GND
53
1
B
1
52
1
B
2
51
V
CC
50
1
B
3
49
1
B
4
48
1
B
5
47
GND
46
1
B
6
45
1
B
7
44
1
B
8
43
2
B
1
42
2
B
2
41
2
B
3
40
GND
39
2
B
4
38
2
B
5
37
2
B
6
36
V
CC
35
2
B
7
34
2
B
8
33
GND
25
2
SAB
26
2
CLKAB
27
2
DIR
28
GND
32
2
SBA
31
2
CLKBA
30
2
OE
29
Product Pin Description
Truth Table
(2)
Product Pin Configuration
e
m
a
N
n
i
P
n
o
it
p
i
r
c
s
e
D
E
O
x
)
W
O
L
e
v
it
c
A
(
st
u
p
n
I
el
b
a
n
E
t
u
p
t
u
O
R
I
D
x
l
o
rt
n
o
C
n
o
it
c
e
ri
D
A
B
K
L
C
x
,
B
A
K
L
C
x
st
u
p
n
I
e
sl
u
P
k
c
o
l
C
A
B
S
x
,
B
A
S
x
st
u
p
n
I
l
o
rt
n
o
C
t
c
el
e
S
x
A
x
st
u
p
n
I
A
r
e
t
si
g
e
R
a
t
a
D
st
u
p
t
u
O
B
r
e
t
si
g
e
R
a
t
a
D
x
B
x
st
u
p
n
I
B
r
e
t
si
g
e
R
a
t
a
D
st
u
p
t
u
O
A
r
e
t
si
g
e
R
a
t
a
D
D
N
G
d
n
u
o
r
G
V
C
C
r
e
w
o
P
56-PIN
V56
A56
Inputs
Data I/O
Function
xOE
xDIR xCLKAB xCLKBA
xSAB xSBA
xAx
xBx
Store A, B Unspecified
(1)
X
X
X
X
X
Input
Unspecified
(1)
Store B, A Unspecified
(1)
X
X
X
X
X
Unspecified
(1)
Input
Isolation
H
X
H or L
H or L
X
X
Input Disable
Input Disable
Store A and B Data
H
X
X
X
Input
Input
Real Time A Data to B Bus
L
H
X
X
L
X
Input
Output
Stored A Data to B Bus
L
H
H or L
X
H
X
Input
Output
Real Time B Data to A Bus
L
L
X
X
X
L
Output
Input
Stored B Data to A Bus
L
L
X
H or L
X
H
Output
Input
Note:
1. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
2. H = High Voltage Level
X = Don't Care
L = Low Voltage Level
= LOW-to-HIGH Transition
4
PS8102A 10/07/98
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PI74ALVCH16646
16-Bit Bus Transceiver and Register
with 3-STATE Outputs
Storage Temperature ............................................................ 65C to +150C
Ambient Temperature with Power Applied .......................... 40C to +85C
Input Voltage Range, V
IN ....................................................
0.5V to V
CC
+4.6V
Output Voltage Range, V
OUT .............................................
0.5V to V
CC
+0.5V
DC Input Voltage ................................................................... 0.5V to +5.0V
DC Output Current................................................................................ 50 mA
Power Dissipation ................................................................................... 1.0W
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40C to +85C, V
CC
= 3.3V 10%)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
s
r
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t
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m
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)
1
(
.
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2
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3
.
2
6
.
3
V
V
H
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3
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g
a
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o
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H
G
I
H
t
u
p
n
I
V
C
C
V
7
.
2
o
t
V
3
.
2
=
7
.
1
V
C
C
V
6
.
3
o
t
V
7
.
2
=
0
.
2
V
L
I )
3
(
e
g
a
tl
o
V
W
O
L
t
u
p
n
I
V
C
C
V
7
.
2
o
t
V
3
.
2
=
7
.
0
V
C
C
V
6
.
3
o
t
V
7
.
2
=
8
.
0
V
N
I
)
3
(
e
g
a
tl
o
V
t
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I
0
V
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C
V
T
U
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)
3
(
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g
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o
V
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p
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0
V
C
C
V
H
O
t
u
p
t
u
O
H
G
I
H
e
g
a
tl
o
V
I
H
O
0
0
1
-
=
m V
,
A
C
C
=
.
x
a
M
o
t
.
n
i
M
V
C
C
2
.
0
-
V
H
I
I
,
V
7
.
1
=
H
O
6
-
=
V
,
A
m
C
C
=
V
3
.
2
0
.
2
V
H
I
I
,
V
7
.
1
=
H
O
2
1
-
=
V
,
A
m
C
C
=
V
3
.
2
7
.
1
V
H
I
I
,
V
0
.
2
=
H
O
2
1
-
=
V
,
A
m
C
C
=
V
7
.
2
2
.
2
V
H
I
I
,
V
0
.
2
=
H
O
2
1
-
=
V
,
A
m
C
C
=
V
0
.
3
4
.
2
V
H
I
I
,
V
0
.
2
=
H
O
4
2
-
=
V
,
A
m
C
C
=
V
0
.
3
0
.
2
V
L
O
t
u
p
t
u
O
W
O
L
e
g
a
tl
o
V
I
L
O
0
0
1
=
m V
,
A
L
I
=
.
x
a
M
o
t
.
n
i
M
2
.
0
V
L
I
I
,
V
7
.
0
=
L
O
6
=
V
,
A
m
C
C
=
V
3
.
2
4
.
0
V
L
I
I
,
V
7
.
0
=
L
O
2
1
=
V
,
A
m
C
C
=
V
3
.
2
7
.
0
V
L
I
I
,
V
8
.
0
=
L
O
2
1
=
V
,
A
m
C
C
=
V
7
.
2
4
.
0
V
L
I
I
,
V
8
.
0
=
L
O
4
2
=
V
,
A
m
C
C
=
V
0
.
3
5
5
.
0
I
H
O )
3
(
t
u
p
t
u
O
H
G
I
H
t
n
e
rr
u
C
V
C
C
V
3
.
2
=
2
1
-
A
m
V
C
C
V
7
.
2
=
2
1
-
V
C
C
V
0
.
3
=
4
2
-
I
L
O )
3
(
t
u
p
t
u
O
W
O
L
t
n
e
rr
u
C
V
C
C
V
3
.
2
=
2
1
V
C
C
V
7
.
2
=
2
1
V
C
C
V
0
.
3
=
4
2
PI74ALVCH16646
16-Bit Bus Transceiver and Register
with 3-STATE Outputs
5
PS8102A 10/07/98
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25C ambient and maximum loading.
3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating.
DC Electrical Characteristics-
Continued (Over the Operating Range, T
A
= 40C to +85C, V
CC
= 3.3V 10%)
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ti
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I
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I
t
n
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rr
u
C
t
u
p
n
I
V
N
I
V
=
C
C
V
,
D
N
G
r
o
C
C
V
6
.
3
=
5
mA
I
N
I
(
HOLD
)
t
u
p
n
I
d
l
o
H
t
n
e
rr
u
C
V
N
I
V
,
V
7
.
0
=
C
C
V
3
.
2
=
5
4
V
N
I
V
,
V
7
.
1
=
C
C
V
3
.
2
=
5
4
-
V
N
I
V
,
V
8
.
0
=
C
C
V
0
.
3
=
5
7
V
N
I
V
,
V
0
.
2
=
C
C
V
0
.
3
=
5
7
-
V
N
I
0
=
o
t
V
,
V
6
.
3
C
C
V
6
.
3
=
0
0
5
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O
)
st
u
p
t
u
O
E
T
A
T
S
-
3
(
t
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e
rr
u
C
t
u
p
t
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O
V
T
U
O
V
=
C
C
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o
,
D
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G
V
C
C
V
6
.
3
=
0
1
I
C
C
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rr
u
C
y
l
p
p
u
S
V
C
C
=
V
6
.
3
I
,
T
U
O
0
= m ,
A
V
N
I
V
r
o
D
N
G
=
C
C
0
4
DI
C
C
t
u
p
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p
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rr
u
C
y
l
p
p
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H
G
I
H
L
T
T
@
V
C
C
V
0
.
3
=
o
t
6
.
3 V
V
t
a
t
u
p
n
I
e
n
O
C
C
-
V
6
.
0
V
t
a
st
u
p
n
I
r
e
h
t
O
C
C
D
N
G
r
o
0
5
7
C
I
st
u
p
n
I
l
o
rt
n
o
C
V
N
I
V
=
C
C
V
,
D
N
G
r
o
C
C
V
3
.
3
=
3
F
p
st
u
p
n
I
a
t
a
D
6
C
O
st
u
p
t
u
O
V
O
V
=
C
C
V
,
D
N
G
r
o
C
C
V
3
.
3
=
7
Timing Requirements
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it
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C
)
1
(
V
C
C
V
2
.
0
V
5
.
2
=
V
C
C
V
7
.
2
=
V
C
C
V
3
.
0
V
3
.
3
=
s
ti
n
U
.
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M
)
2
(
.
x
a
M
.
n
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M
)
2
(
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.
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)
2
(
.
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C
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L
C
y
c
n
e
u
q
e
r
F
k
c
o
l
C
C
L
F
p
0
5
=
R
L
0
0
5
=
W
0
0
5
1
0
0
5
1
0
0
5
1
z
H
M
t
W
n
o
it
a
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e
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u
P
A
B
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L
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o
B
A
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3
.
3
3
.
3
3
.
3
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B
B
6
.
1
7
.
1
4
.
1
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e
m
i
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B
A
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r
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tf
A
A
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o
A
B
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L
C
r
e
tf
A
B
6
.
0
4
.
0
7
.
0
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