1
PS8103 04/03/97
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PI74ALVCH16823
18-Bit Bus-Interface Flip-Flop
with 3-State Outputs
Logic Block Diagram
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced in the Companys advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The 18-bit PI74ALVCH16823 bus-interface flip-flop is designed
for 2.3V to 3.6V V
CC
operation. It features 3-state outputs designed
specifically for driving highly capacitive or relatively low-
impedance loads. This device is particularly suitable for
implementing wider buffer registers, I/O ports, bidirectional bus
drivers with parity, and working registers.
The PI74ALVCH16823 can be used as two 9-bit flip-flops or one
18-bit flip-flop. With the Clock Enable (CLKEN) input LOW, the
D-type flip-flops enter data on the low-to-high transitions of the
clock. Taking CLKEN HIGH disables the clock buffer, thus
latching the outputs. Taking the Clear (CLR) input LOW causes the
Q outputs to go LOW independently of the clock.
A buffered Output Enable (OE) input can be used to place the nine
outputs in either a normal logic state (high or low logic levels) or
high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
The Output Enable (OE) input does not affect the internal operation
of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Product Features
PI74ALVCH16823 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at 40C to +85C
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
2
PS8103 04/03/97
PI74ALVCH16823
18-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
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Inputs
Output
OE
CLR
CLKEN
CLK
D
Q
L
L
X
X
X
L
L
H
L
H
H
L
H
L
L
L
L
H
L
L
X
Q
0
L
H
H
X
X
Q
0
H
X
X
X
X
Z
Product Pin Description
Pin Name
Description
OE
Output Enable Input (Active LOW)
CLR
Clear Input (Active LOW)
CLKEN
Clock Enable Input (Active LOW)
CLK
Clock Input (Active HIGH)
Dx
Data Inputs
Qx
3-State Outputs
GND
Ground
V
CC
Power
Truth Table
(1)
Note:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
= LOW-to-HIGH Transition
Product Pin Configuration
1
1CLR
1OE
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
1CLK
1CLKEN
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2CLKEN
2CLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
25
26
27
28
32
31
30
29
56-Pin
V56
A56
3
PS8103 04/03/97
PI74ALVCH16823
18-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
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DC Electrical Characteristics
(Over the Operating Range, T
A
= 40C to +85C, V
CC
= 3.3V 10%)
s
r
e
t
e
m
a
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a
P
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.
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)
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p
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3
.
2
6
.
3
V
V
H
I
)
3
(
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g
a
tl
o
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G
I
H
t
u
p
n
I
V
C
C
V
7
.
2
o
t
V
3
.
2
=
7
.
1
V
C
C
V
6
.
3
o
t
V
7
.
2
=
0
.
2
V
L
I
)
3
(
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g
a
tl
o
V
W
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p
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V
7
.
2
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V
3
.
2
=
7
.
0
V
C
C
V
6
.
3
o
t
V
7
.
2
=
8
.
0
V
N
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)
3
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g
a
tl
o
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0
V
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C
V
T
U
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)
3
(
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g
a
tl
o
V
t
u
p
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u
O
0
V
C
C
V
H
O
t
u
p
t
u
O
H
G
I
H
e
g
a
tl
o
V
I
H
O
0
0
1
-
=
m V
,
A
C
C
=
.
x
a
M
o
t
.
n
i
M
V
C
C
2
.
0
-
V
H
I
I
,
V
7
.
1
=
H
O
6
-
=
V
,
A
m
C
C
=
V
3
.
2
0
.
2
V
H
I
I
,
V
7
.
1
=
H
O
2
1
-
=
V
,
A
m
C
C
=
V
3
.
2
7
.
1
V
H
I
I
,
V
0
.
2
=
H
O
2
1
-
=
V
,
A
m
C
C
=
V
7
.
2
2
.
2
V
H
I
I
,
V
0
.
2
=
H
O
2
1
-
=
V
,
A
m
C
C
=
V
0
.
3
4
.
2
V
H
I
I
,
V
0
.
2
=
H
O
4
2
-
=
V
,
A
m
C
C
=
V
0
.
3
0
.
2
V
L
O
t
u
p
t
u
O
W
O
L
e
g
a
tl
o
V
I
L
O
0
0
1
=
m V
,
A
L
I
=
.
x
a
M
o
t
.
n
i
M
2
.
0
V
L
I
I
,
V
7
.
0
=
L
O
6
=
V
,
A
m
C
C
=
V
3
.
2
4
.
0
V
L
I
I
,
V
7
.
0
=
L
O
2
1
=
V
,
A
m
C
C
=
V
3
.
2
7
.
0
V
L
I
I
,
V
8
.
0
=
L
O
2
1
=
V
,
A
m
C
C
=
V
7
.
2
4
.
0
V
L
I
I
,
V
8
.
0
=
L
O
4
2
=
V
,
A
m
C
C
=
V
0
.
3
5
5
.
0
I
H
O
)
3
(
t
u
p
t
u
O
H
G
I
H
t
n
e
rr
u
C
V
C
C
V
3
.
2
=
2
1
-
A
m
V
C
C
V
7
.
2
=
2
1
-
V
C
C
V
0
.
3
=
4
2
-
I
L
O
)
3
(
t
u
p
t
u
O
W
O
L
t
n
e
rr
u
C
V
C
C
V
3
.
2
=
2
1
V
C
C
V
7
.
2
=
2
1
V
C
C
V
0
.
3
=
4
2
Storage Temperature ............................................................ 65C to +150C
Ambient Temperature with Power Applied .......................... 40C to +85C
Input Voltage Range, V
IN ....................................................
0.5V to V
CC
+0.5V
Output Voltage Range, V
OUT .............................................
0.5V to V
CC
+0.5V
DC Input Voltage ................................................................... 0.5V to +5.0V
DC Output Current.............................................................................. 100 mA
Power Dissipation ................................................................................... 1.0W
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
4
PS8103 04/03/97
PI74ALVCH16823
18-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
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s
r
e
t
e
m
a
r
a
P
m
o
r
F
)
T
U
P
N
I
(
o
T
)
T
U
P
T
U
O
(
s
n
o
it
i
d
n
o
C
V
C
C
V
2
.
0
V
5
.
2
=
V
C
C
V
7
.
2
=
V
C
C
V
3
.
0
V
3
.
3
=
s
ti
n
U
.
n
i
M
)
2
(
.
x
a
M
.
n
i
M
)
2
(
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x
a
M
.
n
i
M
)
2
(
.
x
a
M
)
2
(
f
X
A
M
0
5
1
0
5
1
0
5
1
t
D
P
K
L
C
Q
C
L
f
p
0
5
=
R
L
0
0
5
=
W
0
.
1
4
.
6
2
.
5
0
.
1
5
.
4
s
n
R
L
C
4
.
1
0
.
6
2
.
5
2
.
1
6
.
4
t
N
E
E
O
0
.
1
5
.
6
7
.
5
0
.
1
8
.
4
t
S
I
D
E
O
8
.
1
6
.
5
7
.
4
3
.
1
5
.
4
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25C ambient and maximum loading.
3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating.
DC Electrical Characteristics-
Continued (Over the Operating Range, T
A
= 40C to +85C, V
CC
= 3.3V 10%)
s
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m
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t
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p
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V
N
I
V
=
C
C
V
,
D
N
G
r
o
C
C
V
6
.
3
=
5
mA
I
N
I
(
HOLD
)
t
u
p
n
I
d
l
o
H
t
n
e
rr
u
C
V
N
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V
,
V
7
.
0
=
C
C
V
3
.
2
=
5
4
V
N
I
V
,
V
7
.
1
=
C
C
V
3
.
2
=
5
4
-
V
N
I
V
,
V
8
.
0
=
C
C
V
0
.
3
=
5
7
V
N
I
V
,
V
0
.
2
=
C
C
V
0
.
3
=
5
7
-
V
N
I
0
=
o
t
V
,
V
6
.
3
C
C
V
6
.
3
=
0
0
5
I
Z
O
)
st
u
p
t
u
O
E
T
A
T
S
-
3
(
t
n
e
rr
u
C
t
u
p
t
u
O
V
T
U
O
V
=
C
C
r
o
,
D
N
G
V
C
C
V
6
.
3
=
0
1
I
C
C
t
n
e
rr
u
C
y
l
p
p
u
S
V
C
C
=
V
6
.
3
I
,
T
U
O
0
= m ,
A
V
N
I
V
r
o
D
N
G
=
C
C
0
4
DI
C
C
t
u
p
n
I
r
e
p
t
n
e
rr
u
C
y
l
p
p
u
S
H
G
I
H
L
T
T
@
V
C
C
V
0
.
3
=
o
t
6
.
3 V
V
t
a
t
u
p
n
I
e
n
O
C
C
-
V
6
.
0
V
t
a
st
u
p
n
I
r
e
h
t
O
C
C
D
N
G
r
o
0
5
7
C
I
st
u
p
n
I
l
o
rt
n
o
C
V
N
I
V
=
C
C
V
,
D
N
G
r
o
C
C
V
3
.
3
=
5
.
4
F
p
st
u
p
n
I
a
t
a
D
5
.
6
C
O
st
u
p
t
u
O
V
O
V
=
C
C
V
,
D
N
G
r
o
C
C
V
3
.
3
=
7
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Switching Characteristics over Operating Range
(1)
5
PS8103 04/03/97
PI74ALVCH16823
18-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
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Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
Timing Requirements over Operating Range
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
Operating Characteristics, T
A
= 25C
r
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m
a
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it
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T
V
C
C
V
2
.
0
V
5
.
2
=
V
C
C
V
3
.
0
V
3
.
3
=
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p
0
5
=
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M
0
1
=
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7
2
0
3
F
p
d
el
b
a
si
D
st
u
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6
1
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1
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V
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C
V
2
.
0
V
5
.
2
=
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V
7
.
2
=
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C
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V
3
.
0
V
3
.
3
=
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k
c
o
l
C
C
L
F
p
0
5
=
R
L
0
0
5
=
W
0
0
5
1
0
0
5
1
0
0
5
1
z
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it
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