1
PS8182A 11/06/00
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PI74ALVCH16841
20-Bit Bus-Interface D-Type Latch
with 3-STATE Outputs
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced in the Companys advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCH16841, a 20-bit bus-interface D-type latch designed
for 2.3V to 3.6V V
CC
operation.
The PI74ALVCH16841 features 3-state outputs designed specifically
for driving highly capacitive or relatively low-impedance loads.
It is particularly suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
The PI74ALVCH16841 can be used as two 10-bit latches or one
20-bit latch (transparent D-type). The device has non-inverting
Data (D) inputs and provides true data at its outputs. While the
Latch Enable (1LE or 2LE) input is HIGH, the Q outputs of the
corresponding 10-bit latch follow the D inputs. When LE is taken
LOW, the Q outputs are latched at the levels set up at the D inputs.
A buffered Output Enable (1OE or 2OE) input can be used to place
the outputs of the corresponding 10-bit latch in either a normal logic
state (high or low logic levels) or a high-impedance state. In that
state, outputs neither load nor drive the bus lines significantly.
The Output Enable (OE) input does not affect the internal operation
of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1D
1OE
C1
1LE
1D1
1Q1
TO NINE OTHER CHANNELS
1
56
55
2
1D
2OE
C1
2LE
2D1
2Q1
TO NINE OTHER CHANNELS
28
29
42
15
Product Features
PI74ALVCH16841 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at 40C to +85C
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
PI74ALVCH16841
20-Bit Bus Interface D-Type Latch
2
PS8182A 11/06/00
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X
Z
Note:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
X = Irrelevant
Product Pin Configuration
Truth Table
(1)
( Each 10-Bit Latch)
Product Pin Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
25
26
27
28
32
31
30
29
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2LE
56-Pin
A, V
PI74ALVCH16841
20-Bit Bus Interface D-Type Latch
3
PS8182A 11/06/00
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Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
Recommended Operating Conditions
(1)
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8
C
Storage Temperature ...........................................................65C to +150C
Ambient Temperature with Power Applied .......................... 40C to +85C
Input Voltage Range, V
IN .......................................................
0.5V to V
CC
+0.5V
Output Voltage Range, V
OUT ................................................
0.5V to V
CC
+0.5V
DC Input Voltage ....................................................................0.5V to +5.0V
DC Output Current ............................................................................. 100mA
Power Dissipation ..................................................................................1.0W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect reliability.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
PI74ALVCH16841
20-Bit Bus Interface D-Type Latch
4
PS8182A 11/06/00
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DC Electrical Characteristics
(Over the Operating Range, T
A
= 40C to +85C, V
CC
= 3.3V 10%)
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25C ambient and maximum loading.
3. Bus Hold maximum dynamic current required to switch the input from one state to another.
4. For I/O ports, the I
OZ
includes the input leakage current.
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PI74ALVCH16841
20-Bit Bus Interface D-Type Latch
5
PS8182A 11/06/00
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4
Switching Characteristics Over Operating Range
(1)
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Timing Requirements over Operating Range
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
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Operating Characteristics, T
A
= 25C
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