1
PS8615 05/10/02
Product Description
Pericom Semiconductors PI74SSTV32852 logic circuit is produced
using the Companys advanced 0.35 micron CMOS technology,
achieving industry leading speed.
All inputs are compatible with the JEDEC standard for SSTL_2,
except the LVCMOS reset (RESET) input. All outputs are SSTL_2,
Class II compatible.
The device operates from a differential clock (CK and CK). Data
registered at the crossing of CK going HIGH, and CK going LOW.
The PI74SSTV32852 supports low-power standby operation. When
RESET is LOW, the differential input receivers are disabled, and
undriven (floating) data, clock and reference voltage (VREF) inputs
are allowed. In addition, when RESET is LOW, all registers are reset,
and all outputs are forced LOW. The LVCMOS RESET input must
always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the LOW state during
power up.
In the DDR DIMM application, RESET is specified to be completely
asynchronous with respect to CK and CK. Therefore, no timing
relationship can be guaranteed between the two. When entering
RESET, the register will be cleared and the outputs will be driven
LOW quickly, relative to the time to disable the differential input
receivers, thus ensuring no glitches on the output. However, when
coming out of RESET, the register will become active quickly, relative
to the time to enable the differential input receivers. When the data
inputs are LOW, and the clock is stable, during the time from the
LOW-to-HIGH transition of RESET until the input receivers
are fully enabled, the design must ensure that the outputs will
remain LOW.
Pericoms PI74SSTV32852 is characterized for operation from
0 to 70C.
Product Features
PI74 SSTV32852 is designed for low-voltage operation,
V
DD
= V
DDQ
= 2.3V to 2.7V
Supports SSTL_2 Class II specifications on outputs
All Inputs are SSTL_2 Compatible, except RESET
which is LVCMOS.
Designed for DDR Memory
Packaging:
114-Ball LFBGA
Logic Block Diagram
Product Pin Description
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74SSTV32852
24-Bit to 48-Bit Registered Buffer
TO 23 OTHER CHANNELS
RESET
CLK
A3
A4
V
REF
D1
T2
R4
D
R
CLK
Q1A
A2
Q1B
A5
CLK
V
R3
e
m
a
N
n
i
P
n
o
it
p
i
r
c
s
e
D
T
E
S
E
R
S
O
M
C
V
L
)
w
o
L
e
v
it
c
A
(
t
e
s
e
R
K
L
C
t
u
p
n
I
l
ai
t
n
e
r
e
ff
i
D
e
v
it
i
s
o
P
,t
u
p
n
I
k
c
o
l
C
K
L
C
t
u
p
n
I
l
ai
t
n
e
r
e
ff
i
D
e
v
it
a
g
e
N
,t
u
p
n
I
k
c
o
l
C
D
t
u
p
n
I
a
t
a
D
Q
t
u
p
t
u
O
a
t
a
D
D
N
G
d
n
u
o
r
G
V
D
D
l
a
n
i
m
o
N
V
5
.
2
,
e
g
a
tl
o
V
y
l
p
p
u
S
e
r
o
C
V
Q
D
D
l
a
n
i
m
o
N
V
5
.
2
,
e
g
a
tl
o
V
y
l
p
p
u
S
t
u
p
t
u
O
V
F
E
R
l
a
n
i
m
o
N
V
5
2
.
1
,
e
g
a
tl
o
V
e
c
n
e
r
e
f
e
R
t
u
p
n
I
s
t
u
p
n
I
s
t
u
p
t
u
O
T
E
S
E
R
K
L
C
K
L
C
D
Q
L
g
n
it
a
o
l
F
r
o
X
g
n
it
a
o
l
F
r
o
X
g
n
it
a
o
l
F
r
o
X
L
H
H
H
L
L
H
H
r
o
L
H
r
o
L
X
o
Q
)
2
(
Truth Table
(1)
Notes:
1. H = High Signal Level; L = Low Signal Level;
= Transition LOW-to-HIGH;
= Transition HIGH-to-LOW
X = Irrelevant or floating
2. Output level before the indicated steady state input conditions were established.
2
PS8615 05/10/02
PI74SSTV32852
24-Bit to 48-Bit
Registered Buffer
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Product Pin Configuration
1
2
3
4
5
6
A
A
2
Q
A
1
Q
K
L
C
K
L
C
B
1
Q
B
2
Q
B
A
3
Q
V
Q
D
D
D
N
G
D
N
G
V
Q
D
D
B
3
Q
C
A
5
Q
A
4
Q
V
Q
D
D
V
Q
D
D
B
4
Q
B
5
Q
D
A
7
Q
A
6
Q
D
N
G
D
N
G
B
6
Q
B
7
Q
E
A
8
Q
D
N
G
V
Q
D
D
V
Q
D
D
D
N
G
B
8
Q
F
A
0
1
Q
A
9
Q
V
Q
D
D
V
Q
D
D
B
9
Q
B
0
1
Q
G
A
2
1
Q
A
1
1
Q
D
N
G
D
N
G
B
1
1
Q
B
2
1
Q
H
A
3
1
Q
V
C
C
V
Q
D
D
V
Q
D
D
V
C
C
B
3
1
Q
J
A
4
1
Q
A
5
1
Q
D
N
G
D
N
G
B
5
1
Q
B
4
1
Q
K
A
7
1
Q
A
6
1
Q
V
Q
D
D
V
Q
D
D
B
6
1
Q
B
7
1
Q
L
A
8
1
Q
A
9
1
Q
D
N
G
D
N
G
B
9
1
Q
B
8
1
Q
M
A
0
2
Q
V
Q
D
D
D
N
G
D
N
G
V
Q
D
D
B
0
2
Q
N
A
2
2
Q
A
1
2
Q
V
Q
D
D
V
Q
D
D
B
1
2
Q
B
2
2
Q
P
A
3
2
Q
V
Q
D
D
D
N
G
D
N
G
V
Q
D
D
B
3
2
Q
R
A
4
2
Q
V
C
C
T
E
S
E
R
V
F
E
R
V
C
C
B
4
2
Q
T
2
D
1
D
6
D
8
1
D
3
1
D
4
1
D
U
4
D
3
D
0
1
D
2
2
D
5
1
D
6
1
D
V
5
D
7
D
1
1
D
3
2
D
9
1
D
7
1
D
W
8
D
9
D
2
1
D
4
2
D
1
2
D
0
2
D
NB Package (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1
2
3
4
5
6
3
PS8615 05/10/02
PI74SSTV32852
24-Bit to 48-Bit
Registered Buffer
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
s
r
e
t
e
m
a
r
a
P
n
o
it
p
i
r
c
s
e
D
.
n
i
M
.
m
o
N
.
x
a
M
s
ti
n
U
V
D
D
e
g
a
tl
o
V
y
l
p
p
u
S
3
.
2
5
.
2
7
.
2
V
V
Q
D
D
e
g
a
tl
o
V
y
l
p
p
u
S
O
/I
3
.
2
5
.
2
7
.
2
V
F
E
R
V
e
g
a
tl
o
V
e
c
n
e
r
e
f
e
R
F
E
R
V
X
5
.
0
=
Q
D
D
5
1
.
1
5
2
.
1
5
3
.
1
V
T
T
e
g
a
tl
o
V
n
o
it
a
n
i
m
r
e
T
V
F
E
R
4
0
.
0
V
F
E
R
V
F
E
R
4
0
.
0
+
V
I
e
g
a
tl
o
V
t
u
p
n
I
0
V
D
D
V
H
I
e
g
a
tl
o
V
t
u
p
n
I
l
e
v
e
L
-
h
g
i
H
C
A
st
u
p
n
I
a
t
a
D
V
F
E
R
0
1
3
+
V
m
V
L
I
e
g
a
tl
o
V
t
u
p
n
I
l
e
v
e
L
-
w
o
L
C
A
V
F
E
R
0
1
3
V
m
V
H
I
e
g
a
tl
o
V
t
u
p
n
I
l
e
v
e
L
-
h
g
i
H
C
D
V
F
E
R
0
5
1
+
V
m
V
L
I
e
g
a
tl
o
V
t
u
p
n
I
l
e
v
e
L
-
w
o
L
C
D
V
F
E
R
0
5
1
V
m
V
H
I
e
g
a
tl
o
V
t
u
p
n
I
l
e
v
e
L
-
h
g
i
H
t
e
s
e
R
7
.
1
V
L
I
e
g
a
tl
o
V
t
u
p
n
I
l
e
v
e
L
-
w
o
L
7
.
0
V
I R
C
e
g
n
a
r
t
u
p
n
i
e
d
o
m
-
n
o
m
m
o
C
K
C
,
K
C
7
9
.
0
3
5
.
1
V
D
I
e
g
a
tl
o
V
t
u
p
n
I
l
ai
t
n
e
r
e
ff
i
D
0
6
3
I
H
O
t
n
e
rr
u
C
t
u
p
t
u
O
l
e
v
e
L
-
h
g
i
H
0
2
A
m
I
L
O
t
n
e
rr
u
C
t
u
p
t
u
O
l
e
v
e
L
-
w
o
L
0
2
T
A
e
r
u
t
a
r
e
p
m
e
T
ri
A
-
e
e
r
F
g
n
it
a
r
e
p
O
0
0
7
C
Recommended Operating Conditions
(4)
Note:
4. The RESET input of the device must be held at V
DD
or GND to ensure proper device operation. The differential inputs must not be
floating, unless RESET is LOW.
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This value is limited to 3.6V Maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
m
e
t
I
s
n
o
it
i
d
n
o
C
/l
o
b
m
y
S
s
g
n
it
a
R
s
ti
n
U
e
r
u
t
a
r
e
p
m
e
t
e
g
a
r
o
t
S
T
g
t
s
0
5
1
o
t
5
6
C
e
g
a
tl
o
v
y
l
p
p
u
S
V
D
D
V
r
o
Q
D
D
6
.
3
o
t
5
.
0
V
e
g
a
tl
o
v
t
u
p
n
I
)
2
,
1
(
V
I
V
o
t
5
.
0
D
D
5
.
0
+
e
g
a
tl
o
v
t
u
p
t
u
O
)
2
,
1
(
V
O
V
o
t
5
.
0
Q
D
D
5
.
0
+
t
n
e
rr
u
c
p
m
al
c
t
u
p
n
I
I
K
I
V
,
I
V
r
o
0
<
I
V
>
D
D
0
5
A
m
t
n
e
rr
u
c
p
m
al
c
t
u
p
t
u
O
I
K
O
V
,
O
V
r
o
0
<
O
V
>
Q
D
D
0
5
t
n
e
rr
u
c
t
u
p
t
u
o
s
u
o
u
n
it
n
o
C
I
O
V
,
O
= 0
V
o
t
Q
D
D
0
5
V
D
D
V
,
Q
D
D
n
i
p
/t
n
e
rr
u
c
D
N
G
r
o
I
D
D
I
,
Q
D
D
I
r
o
D
N
G
0
0
1
e
c
n
a
d
e
p
m
I
l
a
m
r
e
h
T
e
g
a
k
c
a
P
)
3
(
J
A
6
3
W
/
C
4
PS8615 05/10/02
PI74SSTV32852
24-Bit to 48-Bit
Registered Buffer
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
s
r
e
t
e
m
a
r
a
P
s
n
o
it
i
d
n
o
C
t
s
e
T
V
D
D
.
n
i
M
.
p
y
T
)
1
(
.
x
a
M
s
ti
n
U
V
K
I
I
I
= m
8
1 A
V
3
.
2
2
.
1
V
V
H
O
I
H
O
=
0
0
1
A
V
7
.
2
-
V
3
.
2
V
D
D
2
.
0
I
H
O
=
6
1
mA
V
3
.
2
5
9
.
1
V
L
O
I
L
O
=
0
0
1
A
V
7
.
2
-
V
3
.
2
2
.
0
I
H
O
6
1
= mA
V
3
.
2
5
3
.
0
I
I
st
u
p
n
I
ll
A
V
I
V
=
D
D
D
N
G
r
o
V
7
.
2
5
A
I
D
D
)
ci
t
a
t
S
(
y
b
d
n
a
t
S
D
N
G
=
T
E
S
E
R
I
O
0
=
V
7
.
2
0
1
)
ci
t
a
t
S
(
g
n
it
a
r
e
p
O
V
=
T
E
S
E
R
D
D
,
V
I
V
=
)
C
A
(
H
I
V
r
o
)
C
A
(
L
I
5
3
A
m
I
D
D
D
-
g
n
it
a
r
e
p
o
ci
m
a
n
y
D
y
l
n
o
k
c
o
l
c
V
=
T
E
S
E
R
D
D
,
V
I
V
=
)
C
A
(
H
I
V
r
o
)
C
A
(
L
I
,
g
n
i
h
c
ti
w
s
K
C
d
n
a
K
C
.
el
c
y
c
y
t
u
d
%
0
5
6
4
/
A
z
H
M
-
g
n
it
a
r
e
p
O
ci
m
a
n
y
D
t
u
p
n
i
a
t
a
d
h
c
a
e
r
e
p
V
=
T
E
S
E
R
,
D
D
V
I
V
=
)
C
A
(
H
I
V
r
o
)
C
A
(
L
I
,
%
0
5
g
n
i
h
c
ti
w
s
K
C
d
n
a
K
C
t
u
p
n
i
a
t
a
d
e
n
O
.
el
c
y
c
y
t
u
d
k
c
o
l
c
fl
a
h
t
a
g
n
i
h
c
ti
w
s
.
el
c
y
c
y
t
u
d
%
0
5
,y
c
n
e
u
q
e
rf
2
1
/
A
k
c
o
l
c
/
z
H
M
a
t
a
d
t
u
p
n
i
r
H
O
h
g
i
H
t
u
p
t
u
O
I
O
=
A
m
0
2
V
7
.
2
o
t
3
.
2
0
.
7
0
2
r
L
O
w
o
L
t
u
p
t
u
O
I
O
A
m
0
2
=
0
.
7
0
2
C
i
st
u
p
n
I
a
t
a
D
V
I
V
=
F
E
R
V
m
0
5
3
5
.
2
0
.
3
0
.
4
5
.
5
F
p
K
C
d
n
a
K
C
V
R
C
I
V
,
V
5
2
.
1
=
)
P
P
(
I
V
m
0
6
3
=
5
.
6
0
.
8
5
.
9
T
E
S
E
R
V
=
I
V
D
D
D
N
G
r
o
5
.
3
5
3
.
4
0
.
5
DC Electrical Characteristics
(Over the Operating Range, T
A
= 0C to +70C, V
DD
= 2.5V 200mV, V
DDQ
= 2.5V 200mV)
Note:
1. All typical values are at V
DD
= 2.5V, T
A
= 25C.
5
PS8615 05/10/02
PI74SSTV32852
24-Bit to 48-Bit
Registered Buffer
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
r
e
t
e
m
a
r
a
P
)t
u
p
n
I
(
m
o
r
F
)t
u
p
t
u
O
(
o
T
V
D
D
V
2
.
0
V
5
.
2
=
s
ti
n
U
.
n
i
M
.
p
y
T
.
x
a
M
f
x
a
m
0
0
2
z
H
M
t
d
p
K
L
C
,
K
L
C
Q
1
.
1
3
.
3
s
n
t
l
h
p
T
E
S
E
R
Q
0
.
5
Timing Requirements
(over recommended operating free-air temperature range
,
unless otherwise noted)
Switching Characteristics
(Over recommended operating free-air temperature range, unless otherwise noted.)
(See test circuits and switching waveforms).
V
D
D
V
2
.
0
V
5
.
2
=
s
ti
n
U
.
n
i
M
.
x
a
M
f
k
c
o
l
c
y
c
n
e
u
q
e
rf
k
c
o
l
C
0
0
2
z
H
M
t
w
w
o
l
r
o
h
g
i
h
K
C
,
K
C
,
n
o
it
a
r
u
D
e
sl
u
P
5
.
2
s
n
t
t
c
a
.
h
g
i
h
T
E
S
E
R
r
e
tf
a
w
o
l
e
b
t
s
u
m
st
u
p
n
i
a
t
a
d
,
e
m
it
e
v
it
c
a
st
u
p
n
I
l
ai
t
n
e
r
e
ff
i
D
2
2
t
t
c
a
n
i
d
il
a
v
t
a
d
l
e
h
e
b
t
s
u
m
st
u
p
n
i
k
c
o
l
c
d
n
a
a
t
a
d
,
e
m
it
e
v
it
c
a
n
i
st
u
p
n
I
l
ai
t
n
e
r
e
ff
i
D
.
w
o
L
T
E
S
E
R
r
e
tf
a
)
g
n
it
a
o
lf
t
o
n
(
sl
e
v
el
t
u
s
e
t
a
r
w
el
s
t
s
a
f
,
e
m
it
p
u
t
e
S
)
7
,
5
(
K
C
e
r
o
f
e
b
a
t
a
D
K
C
,
5
7
.
0
e
t
a
r
w
el
s
w
o
l
s
,
e
m
it
p
u
t
e
S
)
7
,
6
(
9
.
0
t
h
e
t
a
r
w
el
s
t
s
a
f
,
e
m
it
d
l
o
H
)
7
,
5
(
K
C
r
e
tf
a
a
t
a
D
K
C
,
5
7
.
0
e
t
a
r
w
el
s
w
o
l
s
,
e
m
it
d
l
o
H
)
7
,
6
(
9
.
0
Notes: 5. For data signal input slew rate
1V/ns.
6. For data signal input slew rate
0.5V/ns and <1V/ns.
7. CLK, CLK signals input slew rates are
1V/ns.
This parameter is not necessarily production tested.
6
PS8615 05/10/02
PI74SSTV32852
24-Bit to 48-Bit
Registered Buffer
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Voltage and Current Waveforms
Input Active and Inactive Times
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
Test Circuit and Switching Waveforms
Notes:
8. C
L
includes probe and jig capacitance.
9. I
DD
tested with clock and data inputs held at V
DD
or GND, and I
O
= 0mA.
10. All input pulses are supplied by generators having the following characteristics: PRR
10
MHz, Z
O
= 50 ohms
.
Input slew rate = 1V/ns 20% (unless otherwise specified).
11. The outputs are measured one at a time with one transition per measurement.
12. V
TT
= V
REF
= V
DDQ
/2
13. V
IH
= V
REF
+ 350mV (ac voltage levels) for SSTL inputs. V
IH
= V
DD
for LVCMOS input.
14. V
IL
= V
REF
+ 350mV (ac voltage levels) for SSTL inputs. V
IL
= GND for LVCMOS input.
15. t
PLH
and t
PHL
are the same as t
pd
.
Parameter Measurement Information (V
DD
= 2.5V 0.2V)
V
TT
R
L
= 50 ohms
From Output
Under Test
C
L
= 30pF
(8)
Test Point
Load Circuit
Input
V
IL
V
REF
V
REF
t
w
V
IH
Input
Timing
Input
t
h
t
su
V
IL
V
ICR
V
REF
V
REF
V
I(PP)
V
IH
Voltage Waveforms - Propagation Delay Times
LVCMOS
RESET
Input
Output
t
PHL
V
DD
/2
V
OH
V
IH
V
IL
V
TT
V
OL
Voltage Waveforms - Propagation Delay Times
Timing
Input
Output
V
ICR
t
PLH
t
PHL
V
ICR
V
I(PP)
V
OH
V
TT
V
TT
V
OL
LVCMOS
RESET
Input
I
DD(9)
V
DD
V
DD
/2
t
inact
0V
I
DDH
10%
90%
I
DDL
t
act
7
PS8615 05/10/02
PI74SSTV32852
24-Bit to 48-Bit
Registered Buffer
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
114-Ball LFBGA (NB) Package
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
Ordering Information
e
d
o
C
g
n
i
r
e
d
r
O
e
p
y
T
e
g
a
k
c
a
P
e
g
n
a
R
e
r
u
t
a
r
e
p
m
e
T
B
N
2
5
8
2
3
V
T
S
S
4
7
I
P
A
G
B
F
L
ll
a
B
-
4
1
1
C
0
7
o
t
C
0
0.87mm. Min. (2 layer)
0.90mm. Min. (4 layer)
1.40 Max. (2 layer)
1.45 Max. (4 layer)
0.31 BSC
0.39 0.05
0.80
0.75
PDF 
ZIP